The effect of die attach voiding on the thermal resistance of integrated circuit package
The effect of die attach voiding on the thermal resistance of a hybrid integrated circuit package has been investigated. Voids with precisely controlled geometry, morphology, distribution, and different volume percentages are fabricated in the backside of the silicon chips by modern micro-photolitho...
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| Language: | en_US |
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The University of Arizona.
1987
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| Online Access: | http://hdl.handle.net/10150/276568 |