Showing 1 - 11 results of 11 for search 'ADVANCED DESIGN FOR MANUFACTURING', query time: 0.57s Refine Results
  1. 1
    Design and Implementation of the IP Wrapper for an On-Chip Network
    by Yu-Sheng Lin, 林育生
    Published 2003
    “... highly integrated SoC with advanced manufacturing technology. In the future, the protocol stack like...”
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  2. 2
    VLSI Design of a Timing-Error-Tolerant Microprocessor
    by Guan-Lin Peng, 彭冠霖
    Published 2016
    “...碩士 === 國立東華大學 === 資訊工程學系 === 104 === 　　Due to the ever advancing of semiconductor technology...”
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  3. 3
    Design of Pipelined Circuits for Tolerating Multiple Timing Errors
    by Ｍin-Sheng Gu, 古閔升
    Published 2009
    “... with system-on-chip technology. As the technology of IC manufacturing advances, the number of transistors...”
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  4. 4
    Design and Evaluation of Effective Multicast Routing for Mesh on-Chip Networks
    by Yu-Wen Lai, 賴鈺文
    Published 2016
    “...碩士 === 國立東華大學 === 資訊工程學系 === 104 === For the past few years, the semiconductor manufacturing...”
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  5. 5
    Design of Timing-Error-Tolerant Digital Filters for Various Filter Transformations
    by Zhi-Hong Liang, 梁志鴻
    Published 2014
    “..., the number of transistors in a single chip keeps increasing thanks to the advance of chip manufacturing...”
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  6. 6
    Design of Tree-Based Shortcut Routing for 3D On-Chip Networks with Over-Size IP Cores
    by Tai-Yi Chou, 周泰伊
    Published 2015
    “...碩士 === 國立東華大學 === 資訊工程學系 === 103 === With the rapid advance of chip manufacturing technology, more...”
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  7. 7
    A WRAPPER FOR LOW-POWER ERROR-CORRECTING DATA TRANSMISSION IN ON-CHIP NETWORKS
    by Ying-Ming Huang, 黃英明
    Published 2006
    “... to provide correct, reliable signals in a highly integrated SoC with advanced manufacturing technology...”
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  8. 8
    Delay Padding for Timing-Error-Resilient Pipelines
    by Shih-Jie Hong, 洪士傑
    Published 2010
    “...碩士 === 國立東華大學 === 資訊工程學系 === 98 === With the rapid advance of the semiconductor manufacturing...”
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  9. 9
    Deadlock-Free Algorithmic Routing for 3D Network-on-Chip Architectures
    by Zhi-Jia Gu, 古智嘉
    Published 2016
    “...碩士 === 國立東華大學 === 資訊工程學系 === 104 === With the rapid advance in chip manufacturing technology, more...”
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  10. 10
    Tree-Based Routing for On-Chip Networks with Irregular Mesh Topology
    by Szu-Chen Liu, 劉思辰
    Published 2010
    “...碩士 === 國立東華大學 === 資訊工程學系 === 98 === Owing to rapid advances of semiconductor manufacturing process...”
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  11. 11
    Searching for Efficient Tree-Based Routing in Faulty 2D Mesh On-Chip Networks
    by Chao-Hung Tu, 杜昭弘
    Published 2019
    “...碩士 === 國立東華大學 === 資訊工程學系 === 107 === With continuous advance of semiconductor manufacturing...”
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