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1“... synchronous mirror delay (CSMD) circuit is a kind of digital clock synchronization circuits. The CSMD circuit...”
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2“...碩士 === 國立中央大學 === 電機工程研究所 === 94 === In view of the current SOC systems, a great deal of circuits...”
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3“... synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL) and delay-locked...”
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4“..., the vernier delay line circuit has high circuit resolution but high chip area. In this all digital CMOS self...”
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5“... power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits...”
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6“... circuit. However, resistors and capacitors in the integrated circuits have great variation...”
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7“...-locked loop design. Another is the built-in jitter test technique design. In PLL circuit design, the half...”
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8“... performance, it is gaining more interests in analog circuit design. Also, current-mode circuit takes lower...”
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9“... field of integrated circuits. Phase-locked loop is generally used in clock recovery of communication...”
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10“... integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because...”
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11“... system has forced to design the total digital circuit, but we actually are living in the analogy world...”
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12“...-circuit of integrate system. In this thesis, a fast locking self-calibration PLL is proposed. It can...”
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13“... trend of VLSI circuit is System-on-Chip (SOC). When many systems were integrated into a chip, the system...”
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14“... operation. At the same time the SoC era continuously goes on, integrating digital-to-analog converter (DAC...”
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15“... on the compression standards of JPEG and MPEG. DCT can be implemented to integration circuits thanks to mature...”
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16“... be adopted to the design of high perfor- mance digital processing systems...”
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