Showing 1 - 20 results of 37 for search 'DIGITAL LAYOUT DESIGN', query time: 0.60s Refine Results
  1. 1
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Layout : Circuitos integrados...”
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  2. 2
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Layout : Circuitos integrados...”
    Get full text
    Others
  3. 3
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Layout : Circuitos integrados...”
    Get full text
    Others
  4. 4
    Transistor level automatic generation of radiation-hardened circuits
    by Lazzari, Cristiano
    Published 2009
    Subjects: “...Layout : Circuitos integrados...”
    Get full text
    Others
  5. 5
    Transistor level automatic generation of radiation-hardened circuits
    by Lazzari, Cristiano
    Published 2009
    Subjects: “...Layout : Circuitos integrados...”
    Get full text
    Others
  6. 6
    Transistor level automatic generation of radiation-hardened circuits
    by Lazzari, Cristiano
    Published 2009
    Subjects: “...Layout : Circuitos integrados...”
    Get full text
    Others
  7. 7
    Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo
    by Guex, Jerson Paulo
    Published 2013
    Subjects: “...Cell layout...”
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  8. 8
    Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo
    by Guex, Jerson Paulo
    Published 2013
    Subjects: “...Cell layout...”
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    Others
  9. 9
    Utilizando folding no projeto de portas lógicas robustas à variabilidade de processo
    by Guex, Jerson Paulo
    Published 2013
    Subjects: “...Cell layout...”
    Get full text
    Others
  10. 10
    Geração automática de partes operativas de circuitos VLSI
    by Ziesemer Junior, Adriel Mota
    Published 2009
    Subjects: “...Layout...”
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  11. 11
    Geração automática de partes operativas de circuitos VLSI
    by Ziesemer Junior, Adriel Mota
    Published 2009
    Subjects: “...Layout...”
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  12. 12
    Geração automática de partes operativas de circuitos VLSI
    by Ziesemer Junior, Adriel Mota
    Published 2009
    Subjects: “...Layout...”
    Get full text
    Others
  13. 13
    Síntese automática do leiaute usando o ASTRAN
    by Moura, Gisell Borges
    Published 2018
    Subjects: “...Automatic Layout Synthesis...”
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  14. 14
    Electromigration aware cell design
    by Posser, Gracieli
    Published 2015
    Subjects: “...Physical design...”
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  15. 15
    Electromigration aware cell design
    by Posser, Gracieli
    Published 2015
    Subjects: “...Physical design...”
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  16. 16
    Electromigration aware cell design
    by Posser, Gracieli
    Published 2015
    Subjects: “...Physical design...”
    Get full text
    Others
  17. 17
    Síntese automática do leiaute de redes de transistores
    by Ziesemer Junior, Adriel Mota
    Published 2014
    Subjects: “...2D layout compaction...”
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  18. 18
    Síntese automática do leiaute de redes de transistores
    by Ziesemer Junior, Adriel Mota
    Published 2014
    Subjects: “...2D layout compaction...”
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    Others
  19. 19
    Síntese automática do leiaute de redes de transistores
    by Ziesemer Junior, Adriel Mota
    Published 2014
    Subjects: “...2D layout compaction...”
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    Others
  20. 20
    Trapp : uma ferramenta para particionamento/posicionamento de celulas para metodologia tranca
    by Schermer, Paulo Armando
    Published 2010
    Subjects: “...VLSI design...”
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