Showing 1 - 9 results of 9 for search 'DIGITAL LOGIC DESIGN WITH HDL', query time: 0.64s Refine Results
  1. 1
    Static noise margin analysis for CMOS logic cells in near-threshold
    by Bortolon, Felipe Todeschini
    Published 2018
    Subjects: “...Digital cell design...”
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  2. 2
    Static noise margin analysis for CMOS logic cells in near-threshold
    by Bortolon, Felipe Todeschini
    Published 2018
    Subjects: “...Digital cell design...”
    Get full text
    Others
  3. 3
    Static noise margin analysis for CMOS logic cells in near-threshold
    by Bortolon, Felipe Todeschini
    Published 2018
    Subjects: “...Digital cell design...”
    Get full text
    Others
  4. 4
    Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264
    by Walter, Fábio Leandro
    Published 2013
    Subjects: “...Vídeo digital...”
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    Others
  5. 5
    Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264
    by Walter, Fábio Leandro
    Published 2013
    Subjects: “...Vídeo digital...”
    Get full text
    Others
  6. 6
    Técnicas de baixo consumo para módulos de hardware de codificação de vídeo H.264
    by Walter, Fábio Leandro
    Published 2013
    Subjects: “...Vídeo digital...”
    Get full text
    Others
  7. 7
    Projeto de uma arquitetura dedicada à compressão de imagens no padrão JPEG2000
    by Silva, Sandro Vilela da
    Published 2007
    “.... The architecture for the best trade-off requires 2,090 logic cells of a FPGA device, being able to operate up...”
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    Others
  8. 8
    Projeto de uma arquitetura dedicada à compressão de imagens no padrão JPEG2000
    by Silva, Sandro Vilela da
    Published 2007
    “.... The architecture for the best trade-off requires 2,090 logic cells of a FPGA device, being able to operate up...”
    Get full text
    Others
  9. 9
    Projeto de uma arquitetura dedicada à compressão de imagens no padrão JPEG2000
    by Silva, Sandro Vilela da
    Published 2007
    “.... The architecture for the best trade-off requires 2,090 logic cells of a FPGA device, being able to operate up...”
    Get full text
    Others
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