Showing 1 - 6 results of 6 for search 'DIGITAL LOGIC DESIGN WITH HDL', query time: 0.89s Refine Results
  1. 1
    Technology mapping for virtual libraries based on cells with minimal transistor stacks
    by Marques, Felipe de Souza
    Published 2009
    Subjects: “...Logic synthesis...”
    Get full text
    Others
  2. 2
    Technology mapping for virtual libraries based on cells with minimal transistor stacks
    by Marques, Felipe de Souza
    Published 2009
    Subjects: “...Logic synthesis...”
    Get full text
    Others
  3. 3
    Technology mapping for virtual libraries based on cells with minimal transistor stacks
    by Marques, Felipe de Souza
    Published 2009
    Subjects: “...Logic synthesis...”
    Get full text
    Others
  4. 4
    Um algoritmo formal para remoção de redundâncias
    by Marques, Felipe de Souza
    Published 2007
    “... lista de falhas, vetores de teste e cobertura de falhas. === Algorithms for digital circuit design aim...”
    Get full text
    Others
  5. 5
    Um algoritmo formal para remoção de redundâncias
    by Marques, Felipe de Souza
    Published 2007
    “... lista de falhas, vetores de teste e cobertura de falhas. === Algorithms for digital circuit design aim...”
    Get full text
    Others
  6. 6
    Um algoritmo formal para remoção de redundâncias
    by Marques, Felipe de Souza
    Published 2007
    “... lista de falhas, vetores de teste e cobertura de falhas. === Algorithms for digital circuit design aim...”
    Get full text
    Others
Search Tools: Get RSS Feed — Email this Search