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4by Llanos, Roger Vicente Caputo“... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
Published 2017
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5by Llanos, Roger Vicente Caputo“... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
Published 2017
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6by Llanos, Roger Vicente Caputo“... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
Published 2017
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7by Neuberger, Gustavo“... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
Published 2008
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8by Neuberger, Gustavo“... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
Published 2008
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9by Neuberger, Gustavo“... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
Published 2008
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10by Bastos, Rodrigo PossamaiSubjects: “...Integrated circuit design...”
Published 2007
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11by Bastos, Rodrigo PossamaiSubjects: “...Integrated circuit design...”
Published 2007
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12by Bastos, Rodrigo PossamaiSubjects: “...Integrated circuit design...”
Published 2007
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13by Guareschi, William do NascimentoSubjects: “...Programmable logic devices...”
Published 2016
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14by Guareschi, William do NascimentoSubjects: “...Programmable logic devices...”
Published 2016
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15by Guareschi, William do NascimentoSubjects: “...Programmable logic devices...”
Published 2016
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19by Kastensmidt, Fernanda Gusmão de Lima“... to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based...”
Published 2007
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20by Kastensmidt, Fernanda Gusmão de Lima“... to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based...”
Published 2007
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