Showing 1 - 20 results of 66 for search 'DIGITAL LOGIC DESIGN WITH HDL', query time: 0.82s Refine Results
  1. 1
    Low-power design using networks of transistors
    by Scartezzini, Gerson
    Published 2015
    Subjects: “...Computer-aided design...”
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  2. 2
    Low-power design using networks of transistors
    by Scartezzini, Gerson
    Published 2015
    Subjects: “...Computer-aided design...”
    Get full text
    Others
  3. 3
    Low-power design using networks of transistors
    by Scartezzini, Gerson
    Published 2015
    Subjects: “...Computer-aided design...”
    Get full text
    Others
  4. 4
    Voltage scaling interfaces for multi-voltage digital systems
    by Llanos, Roger Vicente Caputo
    Published 2017
    “... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
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  5. 5
    Voltage scaling interfaces for multi-voltage digital systems
    by Llanos, Roger Vicente Caputo
    Published 2017
    “... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
    Get full text
    Others
  6. 6
    Voltage scaling interfaces for multi-voltage digital systems
    by Llanos, Roger Vicente Caputo
    Published 2017
    “... alimentação. === Multiple Voltage Digital Systems exploit the concept of voltage scaling by applying different...”
    Get full text
    Others
  7. 7
    Protecting digital circuits against hold time violations due to process variations
    by Neuberger, Gustavo
    Published 2008
    “... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
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  8. 8
    Protecting digital circuits against hold time violations due to process variations
    by Neuberger, Gustavo
    Published 2008
    “... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
    Get full text
    Others
  9. 9
    Protecting digital circuits against hold time violations due to process variations
    by Neuberger, Gustavo
    Published 2008
    “... of flip-flops in short logic paths, which are generated by clock-edge uncertainties in synchronous designs...”
    Get full text
    Others
  10. 10
    Design of a soft-error robust microprocessor
    by Bastos, Rodrigo Possamai
    Published 2007
    Subjects: “...Integrated circuit design...”
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  11. 11
    Design of a soft-error robust microprocessor
    by Bastos, Rodrigo Possamai
    Published 2007
    Subjects: “...Integrated circuit design...”
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  12. 12
    Design of a soft-error robust microprocessor
    by Bastos, Rodrigo Possamai
    Published 2007
    Subjects: “...Integrated circuit design...”
    Get full text
    Others
  13. 13
    Desenvolvimento de uma plataforma para teste e controle de cargas-úteis baseada em arquitetura reconfigurável
    Subjects: “...Programmable logic devices...”
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  14. 14
    Desenvolvimento de uma plataforma para teste e controle de cargas-úteis baseada em arquitetura reconfigurável
    Subjects: “...Programmable logic devices...”
    Get full text
    Others
  15. 15
    Desenvolvimento de uma plataforma para teste e controle de cargas-úteis baseada em arquitetura reconfigurável
    Subjects: “...Programmable logic devices...”
    Get full text
    Others
  16. 16
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Static CMOS logic gates...”
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  17. 17
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Static CMOS logic gates...”
    Get full text
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  18. 18
    Automatic layout generation of static CMOS circuits targeting delay and power
    by Lazzari, Cristiano
    Published 2007
    Subjects: “...Static CMOS logic gates...”
    Get full text
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  19. 19
    Designing single event upset mitigation techniques for large SRAM-Based FPGA components
    “... to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based...”
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  20. 20
    Designing single event upset mitigation techniques for large SRAM-Based FPGA components
    “... to FPGAs. The TMR technique was first tested in the Virtex® FPGA architecture by using a small design based...”
    Get full text
    Others
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