Showing 1 - 12 results of 12 for search 'DIGITAL LOGIC DESIGN WITH HDL', query time: 1.51s Refine Results
  1. 1
    Arquitetura de co-projeto hardware/software para implementação de um codificador de vídeo escalável padrão H.264/SVC
    by Husemann, Ronaldo
    Published 2012
    Subjects: “...Vídeo digital...”
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  2. 2
    Arquitetura de co-projeto hardware/software para implementação de um codificador de vídeo escalável padrão H.264/SVC
    by Husemann, Ronaldo
    Published 2012
    Subjects: “...Vídeo digital...”
    Get full text
    Others
  3. 3
    Arquitetura de co-projeto hardware/software para implementação de um codificador de vídeo escalável padrão H.264/SVC
    by Husemann, Ronaldo
    Published 2012
    Subjects: “...Vídeo digital...”
    Get full text
    Others
  4. 4
    Risco : microprocessador RISC CMOS de 32 bits
    by Junqueira, Alexandre Ambrozi
    Published 2010
    Subjects: “...Design...”
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    Others
  5. 5
    Risco : microprocessador RISC CMOS de 32 bits
    by Junqueira, Alexandre Ambrozi
    Published 2010
    Subjects: “...Design...”
    Get full text
    Others
  6. 6
    Risco : microprocessador RISC CMOS de 32 bits
    by Junqueira, Alexandre Ambrozi
    Published 2010
    Subjects: “...Design...”
    Get full text
    Others
  7. 7
    Avaliação de desempenho de partes de controle de circuitos integrados
    by Hubscher, Pedro Inacio
    Published 2010
    “... are used for implementation (PLA and gate matrix). Both of them use the same design rules. The analysis...”
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    Others
  8. 8
    Avaliação de desempenho de partes de controle de circuitos integrados
    by Hubscher, Pedro Inacio
    Published 2010
    “... are used for implementation (PLA and gate matrix). Both of them use the same design rules. The analysis...”
    Get full text
    Others
  9. 9
    Avaliação de desempenho de partes de controle de circuitos integrados
    by Hubscher, Pedro Inacio
    Published 2010
    “... are used for implementation (PLA and gate matrix). Both of them use the same design rules. The analysis...”
    Get full text
    Others
  10. 10
    Convolutional neural network reliability on an APSoC platform a traffic-sign recognition case study
    by Lopes, Israel da Costa
    Published 2017
    “...) Hardware Description Language (VHDL) automatic generator was developed to reduce the design time associated...”
    Get full text
    Others
  11. 11
    Convolutional neural network reliability on an APSoC platform a traffic-sign recognition case study
    by Lopes, Israel da Costa
    Published 2017
    “...) Hardware Description Language (VHDL) automatic generator was developed to reduce the design time associated...”
    Get full text
    Others
  12. 12
    Convolutional neural network reliability on an APSoC platform a traffic-sign recognition case study
    by Lopes, Israel da Costa
    Published 2017
    “...) Hardware Description Language (VHDL) automatic generator was developed to reduce the design time associated...”
    Get full text
    Others
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