Showing 1 - 20 results of 21 for search 'DIGITAL SIGNAL PROCESSING', query time: 1.10s Refine Results
  1. 1
    by Chenn-Jung Huang, 黃振榮
    Published 2000
    ... of signal processing technology has naturally been accompanied by a corresponding development of arithmetic...
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  2. 2
    by Yi-Jie Hsieh, 謝依潔
    Published 2013
    ...碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === This thesis consists of two topics, i.e., a process...
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  3. 3
    by Tsung-Yi Tsai, 蔡宗毅
    Published 2019
    ... process corners. Thus, status signals will be turned off after the data transmission of the output signal...
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  4. 4
    ...碩士 === 國立中正大學 === 電機工程所 === 95 === This paper presents new techniques to implement direct digital...
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  5. 5
    by Pei-Tong Liao, 廖沛彤
    Published 2018
    ... process, and it is a programable system which is combined with a PLL circuit for clock generation...
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  6. 6
    by Yi-Wei Chen, 陳易緯
    Published 2002
    ... for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which...
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  7. 7
    by Chien-Chih Hung, 洪健智
    Published 2005
    ...-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three...
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  8. 8
    by Jian-Sing Liou, 劉建興
    Published 2007
    ...-mentation amplifier (IA) for neural signal sensing and a low-power implantable bladder pressure monitor SOC...
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  9. 9
    by Yu-cheng Lu, 呂育誠
    Published 2009
    ...(All Digital Frequency Synthesizer)using a Flying Adder architecture. The second one is a low-power...
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  10. 10
    by Jian-ming Huang, 黃建銘
    Published 2008
    ... frequency signal, we propose a direct digital frequency synthesizer (DDFS) based on the quadruple angle...
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  11. 11
    by Ying-Yu Shen, 沈穎昱
    Published 2007
    ... with the DVB-H standard. The received DVB-H signal is processed by an RF front-end and the following analog...
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  12. 12
  13. 13
    by Jhih-cheng You, 尤志成
    Published 2018
    ... Signal Based LDMOS AI_USG Polycide 2P3M (T50UHV) Process to justify the design theory and expected...
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  14. 14
    by Chi-Chung Huang, 黃祺峻
    Published 2009
    ...’ physiological signal could be recorded without restricting their mobility. Moreover, integration of several...
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  15. 15
    by Wei-chih Chang, 張威銍
    Published 2008
    ... generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V...
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  16. 16
    by Tuo-yu Yao, 姚拓宇
    Published 2009
    ... single coil for bio-implants. A voltage buffer implemented in 2P4M 0.35 μm CMOS process, which...
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  17. 17
    by Jun-Han Wu, 吳俊翰
    Published 2008
    ... the pressure in a long-term mode with an automatic sleeping mechanism for power saving. The signal generated...
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  18. 18
    by Pai-Li Liu, 劉百莉
    Published 2005
    ... power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter...
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  19. 19
    by Shao-Bin Tseng, 曾紹賓
    Published 2011
    ... contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC...
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  20. 20
    by Tie-Yan Chang, 張鐵諺
    Published 2007
    ... can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS...
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