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1“... of signal processing technology has naturally been accompanied by a corresponding development of arithmetic...”
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2“...碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === This thesis consists of two topics, i.e., a process...”
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3“... process corners. Thus, status signals will be turned off after the data transmission of the output signal...”
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4by wen-ko wuang, 黃文科“...碩士 === 國立中正大學 === 電機工程所 === 95 === This paper presents new techniques to implement direct digital...”
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5“... process, and it is a programable system which is combined with a PLL circuit for clock generation...”
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6“... for analog and digital communication. It converts an analog signal into an 8-bit digital signal, which...”
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7“...-end circuit of DVB-T receivers. The proposed AAF is controlled by digital signals to provide three...”
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8“...-mentation amplifier (IA) for neural signal sensing and a low-power implantable bladder pressure monitor SOC...”
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9“...(All Digital Frequency Synthesizer)using a Flying Adder architecture. The second one is a low-power...”
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10“... frequency signal, we propose a direct digital frequency synthesizer (DDFS) based on the quadruple angle...”
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11“... with the DVB-H standard. The received DVB-H signal is processed by an RF front-end and the following analog...”
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12“... Mixed Signal/RF process to justify the design theory and performance. Besides, a switching power...”
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13“... Signal Based LDMOS AI_USG Polycide 2P3M (T50UHV) Process to justify the design theory and expected...”
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14“...’ physiological signal could be recorded without restricting their mobility. Moreover, integration of several...”
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15“... generator. The proposed design can transmit and receive digital signals with voltage levels of 5/3.3/1.8 V...”
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16“... single coil for bio-implants. A voltage buffer implemented in 2P4M 0.35 μm CMOS process, which...”
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17“... the pressure in a long-term mode with an automatic sleeping mechanism for power saving. The signal generated...”
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18“... power design of 8-bit ANT-based pipelining CLA. The second one is a small digital to analog converter...”
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19“... contains a novel ASK demodulator which converts the ASK signals into digital signals reliably. The SOC...”
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20“... can transmit and receive the digital signals with voltage levels of 5/3.3/1.8 V. By using stacked PMOS...”
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