“... chip. The potential destructive nature of ESD in CMOS ICs becomes serious and the design of ESD...”
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“...碩士 === 國立交通大學 === 電機學院IC設計產業專班 === 95 === This thesis focuses on the ESD protection design for high...”
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“... are proposed to improve ESD robustness of the high-voltage IC products fabricated in CMOS technology...”
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“... (ICs), because it includes all of fundamental cells to construct the ICs. In the cell library...”
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“... in high-voltage CMOS ICs will be an important challenge to on-chip ESD protection design for high-voltage...”
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“... input design, the IC with 3.3-V power supply needs to accept 5-V input signals. A substrate-triggered...”
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“... issues in IC products, must be taken into consideration during the design phase of all IC products. Most...”
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“... with the different ESD implantations and layout design on gate-grounded NMOS (GGNMOS) and gate-VDD PMOS...”
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“... and current-triggering circuits are realized to protect the CMOS ICs. First, a complementary...”
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