Showing 1 - 20 results of 28 for search 'INTEGRATED CIRCUIT DESIGN', query time: 0.53s Refine Results
  1. 1
    Analysis and Design of New Charge Pump Circuit
    by Chung-Yu Chang, 張仲宇
    Published 2003
    “...碩士 === 淡江大學 === 電機工程學系 === 91 === Recently, low-voltage low-power integrated circuits are used...”
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  2. 2
    Low-Voltage High-Speed Dynamic Circuit Research and Design
    by Yung-Chong Huang, 黃永中
    Published 2000
    “... VLSI design and high-speed microprocessor, low voltage high performance integrated circuit has become...”
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  3. 3
    Design and Implementation of Adaptive Equalizer and Clock Synchronization Circuits for Wired-Line Transceivers
    by Yu-Chang Tsai, 蔡玉章
    Published 2011
    “..., low-voltage and low power consumption integrated circuits have become more and more important. In high...”
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  4. 4
    Design of CMOS Transmitter Circuit for 2.5Gbps NRZ Data Transmission
    by shin-Syong Guo, 郭世雄
    Published 2005
    “...碩士 === 國立中央大學 === 電機工程研究所 === 93 === Design of CMOS Transmitter Circuit for 2.5Gps NRZ Data...”
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  5. 5
    Design and Implementation of All-Digital High Precision Fast Locking Clock Synchronization Circuits
    by Kai-Wei Hong, 洪凱尉
    Published 2011
    “... longer. Some application-specific integrated chips (ASICs) or silicon intellectual properties (IPs) might...”
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  6. 6
    All-Digital Arbitrary Duty-Cycle Synchronous Mirror Delay Circuits
    by Chen-Lung Wu, 伍振龍
    Published 2006
    “...碩士 === 國立中央大學 === 電機工程研究所 === 94 === In view of the current SOC systems, a great deal of circuits...”
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  7. 7
    Built-In Jitter Measurement Circuit for 2.5GHz Phase-Locked Loop
    by Pei-yi Jian, 簡佩怡
    Published 2007
    “...(SOC) is the current trend of VLSI circuit. When many systems were integrated into a chip...”
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  8. 8
    An All Digital Fast Locked Four-Phase Synchronous Mirror Delay Circuit
    by Yin-ping Yeh, 葉蔭平
    Published 2012
    “... synchronization circuit plays an important role in designing SoC system. Phase-Locked loop (PLL) and delay-locked...”
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  9. 9
    All Digital CMOS Self-sample Vernier Delay Line Circuit for Clock Jitter Measurement
    by Chan-Wei Huang, 黃展緯
    Published 2006
    “.... The proposed circuit is designed in TSMC 0.35um 2P4M CMOS process. The resolution of one-period-delay circuit...”
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  10. 10
    GHz PLL with Built-In Jitter Test Design
    by Shu-Yu Jiang, 江書育
    Published 2003
    “...-locked loop design. Another is the built-in jitter test technique design. In PLL circuit design, the half...”
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  11. 11
    Design and Application of High Accuracy and High Impedance Current Mirror
    by Chi-Che Chen, 陳麒哲
    Published 2002
    “... performance, it is gaining more interests in analog circuit design. Also, current-mode circuit takes lower...”
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  12. 12
    Design and Implementation of Key Technologies Applied to High-Speed Serial Links
    by Yo-Hao Tu, 涂祐豪
    Published 2018
    “...博士 === 國立中央大學 === 電機工程學系 === 106 === 　Advance in integrated circuit fabrication technology...”
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  13. 13
    Design and Analysis of a Novel All Digital Phase-Locked Loop
    by Ta-Wei Liu, 劉大維
    Published 2002
    “... circuit. However, resistors and capacitors in the integrated circuits have great variation...”
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  14. 14
    Low-Power and Low Phase-Error Phase-Locked Loop Design
    by Lin-Jiunn Tzou, 鄒林俊
    Published 2000
    “... field of integrated circuits. Phase-locked loop is generally used in clock recovery of communication...”
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  15. 15
    Design of Low-Jitter Adaptive Bandwidth PLL Based on Self-Biased Techniques
    by Ching-Wen Lai, 賴敬文
    Published 2005
    “... integrated (VLSI) circuit increases fast, there are more and more transistors in the unit area, because...”
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  16. 16
    Design and Application of New Double Edge Triggered D-type Flip-Flop
    by Yung-Hsiang Lin, 林永祥
    Published 2003
    “.... Because of the increased circuit complexity, power consumption becomes a key design consideration of any...”
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  17. 17
    Design and Implementation of Low-Power GHz CMOS Half-Digital PLL and High-Driving Digital Buffer
    by Wei-Bin Yang, 楊維斌
    Published 2003
    “... power distribution networks are important for high-speed deep submicrometer CMOS integrated circuits...”
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  18. 18
    A 100MHz-1GHz Adaptive Bandwidth Phase-locked Loop Designed in 90nm Process
    by Kai-Fei Chang, 張凱斐
    Published 2006
    “... integrated (VSLI) circuit increases fast, there are more and more transistors in the unit area, because...”
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  19. 19
    An 80-200MHz Continuous Time Low-pass Filter by Design of Highly Linear Tunable Fully Differential Transcondutor
    by Wen-Fang Yu, 游文芳
    Published 2004
    “... system has forced to design the total digital circuit, but we actually are living in the analogy world...”
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  20. 20
    A 2.5GHz Fast Locking Self-Calibration Phase-Locked Loop Designed in 90nm Process
    by Yu-Fen Lin, 林鈺芬
    Published 2008
    “...-circuit of integrate system. In this thesis, a fast locking self-calibration PLL is proposed. It can...”
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