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1“... translation systems. First, for the training phase, to improve template learning accuracy from parallel...”
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2“...-alone system. Additionally, when system is going to commercialize, DSP...”
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3“... present a high performance VLSI speech recognizer with high recognition rate. First, a prototype system...”
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4“... system, such as TTS system, toys, electronic books, etc. For the portable speech synthesis devices, how...”
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5“... whole speech recognition system is designed with modules. We bring up a VLSI architecture of the whole...”
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6“... applications , such as high definition television , disk operation system , video coding...”
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7“... be used to design a multi-channel coding system. However, if high-speed operations are not necessary...”
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8“... and spectral subtraction methods. In the design of VLSI architecture, a hardware design of 2D discrete wavelet...”
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9“... speech/music discrimination system which works well under noisy environment. In our system, a statistical...”
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10“... interpolation, the method can avoid the COS operation and let the hardware system only create one LSP-x ROM...”
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11“... system, VLSI architecture design and Hardware/Software co-design. In smart home, the speaker recognition...”
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12“...-in extraction, recognition, and training (ERT) core. For VLSI design (here ASSR system), the hardware cost...”
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13“... popular. Conventional VLSI designs focus on the enhancement of single component; in addition, most chip...”
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14“... proposed. The designs are implemented using the Integrated Systems Engineering (ISE) 5.1i software [3] on a...”
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15“... sound recognizer. Moreover, related VLSI architectures for this sound recognition system are also...”
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16“... regular and suit for VLSI design,(3)the final solution(the best match block) is closed...”
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17“...碩士 === 國立成功大學 === 電機工程學系碩博士班 === 92 === In this thesis, we describe a design of signal subspace...”
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18“...博士 === 國立成功大學 === 電機工程學系碩博士班 === 91 === In this dissertation, we propose several VLSI...”
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19“...博士 === 國立成功大學 === 資訊工程學系 === 85 === In this disserpation, the efficient and flexible VLSI...”
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