Design and Evaluation of High-Speed Overcurrent and Short-Circuit Detection Circuits With High Noise Margin for WBG Power Semiconductor Devices

• 出版年: IEEE Access
• 主要な著者: Hae-Chan Park, Myeong-Jun Cha, Seon-Ho Jeon, Rae-Young Kim
• フォーマット: 論文
• 言語: 英語
• 出版事項: IEEE 2024-01-01
• 主題: Wide bandgap (WBG); device under test (DUT); SiC MOSFETs; GaN HEMTs; double pulse test (DPT); fault under load (FUL)
• オンライン･アクセス: https://ieeexplore.ieee.org/document/10385085/

Currently, wide bandgap (WBG) power semiconductor devices such as low-resistance SiC MOSFETs and GaN HEMTs are being utilized extensively to achieve high efficiency. However, securing a sufficient margin voltage between the drain–source sensing voltage and the trigger voltage of the device under test (DUT) during normal operation becomes challenging due to their low threshold voltage, thereby increasing the risk of incorrect detection. This study proposes an overcurrent detection circuit with high noise immunity for driving SiC MOSFETs in inverters and converters. The proposed circuit can detect not only short-circuit conditions but also overcurrent. Furthermore, this study presents a design approach for securing ample margin voltage between the drain–source sensing voltage and trigger voltage, validated through double pulse test (DPT), fault under load (FUL), and hard switching fault (HSF) experiments. The experimental results indicate that the proposed circuit secures margin voltage during normal operation and quickly deactivates the device in case of failure. Additionally, it was confirmed experimentally that the proposed circuit achieves a current sensing sensitivity of 92.667mV/A and can reliably detect faults within 35ns under FUL conditions and within 210ns under HSF conditions.