| Summary: | This paper proposes a low-noise interface application-specific integrated circuit (ASIC) for a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) which operates in force-to-rebalance (FTR) mode. The ASIC employs an analog closed-loop control scheme which incorporates a self-excited drive loop, a rate loop and a quadrature loop. A ΣΔ modulator and a digital filter are also contained in the design to digitize the analog output besides the control loops. The clocks for the modulator and digital circuits are both generated by the self-clocking circuit, which avoids the requirement of additional quartz crystal. A system-level noise model is established to determine the contribution of each noise source in order to reduce the noise at the output. A noise optimization solution suitable for chip integration is proposed based on system-level analysis, which can effectively avoid the effects of the 1/f noise of the PI amplifier and the white noise of the feedback element. A performance of 0.0075°/√h angle random walk (ARW) and 0.038°/h bias instability (BI) is achieved using the proposed noise optimization method. The ASIC is fabricated in a 0.35 μm process with a die area of 4.4 mm × 4.5 mm and power consumption of 50 mW.
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