توثيق جمعية علم النفس الأمريكية APA (الطبعة السابعة)

Jujjavarapu, R. M., & Poulose, A. (2022, September). Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 nm HVT Cells. Signals.

توثيق أسلوب شيكاغو (الطبعة السابعة عشر)

Jujjavarapu, Raj Mouli, و Alwin Poulose. "Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 Nm HVT Cells." Signals Sep. 2022.

توثيق جمعية اللغة المعاصرة MLA (الإصدار التاسع)

Jujjavarapu, Raj Mouli, و Alwin Poulose. "Verilog Design, Synthesis, and Netlisting of IoT-Based Arithmetic Logic and Compression Unit for 32 Nm HVT Cells." Signals, Sep. 2022.