| Summary: | As the complexity of convolutional neural networks (CNN) continues to increase, efficient deployment on computationally constrained hardware platforms has become a significant challenge. Against this backdrop, field-programmable gate arrays (FPGA) emerge as an up-and-coming CNN acceleration platform due to their inherent energy efficiency, reconfigurability, and parallel processing capabilities. This paper establishes a systematic analytical framework to explore CNN optimization strategies on FPGA from both algorithmic and hardware perspectives. It emphasizes co-design methodologies between algorithms and hardware, extending these concepts to other embedded system applications. Furthermore, the paper summarizes current performance evaluation frameworks to assess the effectiveness of acceleration schemes comprehensively. Finally, building upon existing work, it identifies key challenges in this field and outlines future research directions.
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