Design of an SoC Based on 32-Bit RISC-V Processor with Low-Latency Lightweight Cryptographic Cores in FPGA

The security of Internet of Things (IoTs) devices in recent years has created interest in developing implementations of lightweight cryptographic algorithms for such systems. Additionally, open-source hardware and field-programable gate arrays (FPGAs) are gaining traction via newly developed tools,...

Full description

Bibliographic Details
Published in:	Future Internet
Main Authors:	Khai-Minh Ma, Duc-Hung Le, Cong-Kha Pham, Trong-Thuc Hoang
Format:	Article
Language:	English
Published:	MDPI AG 2023-05-01
Subjects:	system-on-chip FPGA RISC-V VexRiscv lightweight cryptography
Online Access:	https://www.mdpi.com/1999-5903/15/5/186

Similar Items

Implementation of FPGA based 32-bit RISC-V processor
by: Kamer Kırali, et al.
Published: (2025-10-01)

NVPE: An FPGA-Based Non-Volatile Processor Emulator for Intermittent Computing
by: Idris Somoye, et al.
Published: (2024-05-01)

CREATOR: An Educational Integrated Development Environment for RISC-V Programming
by: Diego Camarmas-Alonso, et al.
Published: (2024-01-01)

Optimized Hardware-Software Co-Design for Kyber and Dilithium on RISC-V SoC FPGA
by: Tengfei Wang, et al.
Published: (2024-07-01)

An Educational RISC-V-Based 16-Bit Processor
by: Jecel Mattos de Assumpção, et al.
Published: (2024-11-01)

FAC-V: An FPGA-Based AES Coprocessor for RISC-V
by: Tiago Gomes, et al.
Published: (2022-09-01)

Optimised Extension of an Ultra-Low-Power RISC-V Processor to Support Lightweight Neural Network Models
by: Qiankun Liu, et al.
Published: (2025-04-01)

Optimized Implementation of PIPO Block Cipher on 32-Bit ARM and RISC-V Processors
by: Youngbeom Kim, et al.
Published: (2022-01-01)

A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation
by: Onur Toker
Published: (2023-11-01)

RISC Conversions for LNS Arithmetic in Embedded Systems
by: Peter Drahoš, et al.
Published: (2020-07-01)

Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems
by: Hyunjae Park, et al.
Published: (2025-01-01)

8-bit softcore microprocessor with dual accumulator designed to be used in FPGA
by: Fernando Martinez Santa, et al.
Published: (2018-04-01)

Multi-Functional Resource-Constrained Elliptic Curve Cryptographic Processor
by: Binh Kieu Do-Nguyen, et al.
Published: (2023-01-01)

A Real-Time Cache Side-Channel Attack Detection System on RISC-V Out-of-Order Processor
by: Anh-Tien Le, et al.
Published: (2021-01-01)

High-Efficiency Multi-Standard Polynomial Multiplication Accelerator on RISC-V SoC for Post-Quantum Cryptography
by: Duc-Thuan Dam, et al.
Published: (2024-01-01)

Design of SoC System for Convolution Acceleration Based on RISC-V Processor
by: ZHANG Kunning, ZHAO Shuo, HE Hu, DENG Ning, YANG Xu
Published: (2021-04-01)

Design and Implementation of RISC-Ⅴ Extended Ⅰnstruction Set Supporting FPGA Dynamic Reconfiguration
by: ZHOU Xuanjin, CAI Gang, HUANG Zhihong
Published: (2025-05-01)

Realization of Authenticated One-Pass Key Establishment on RISC-V Micro-Controller for IoT Applications
by: Tuan-Kiet Dang, et al.
Published: (2024-05-01)

Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers
by: Peter Jamieson, et al.
Published: (2022-08-01)

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor
by: Donald E. Owen, et al.
Published: (2022-08-01)

Design of Ultra-Low-Power RISC-V Dedicated Processor for IToF Sensor
by: HUANG Zhengwei, LIU Hongwei, XU Yuan
Published: (2022-09-01)

AESware: Developing AES-enabled low-power multicore processors leveraging open RISC-V cores with a shared lightweight AES accelerator
by: Eunjin Choi, et al.
Published: (2024-12-01)

RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO<sub>2</sub> Concentration Sensing
by: Ricardo Núñez-Prieto, et al.
Published: (2023-07-01)

Design and verification of AES cryptographic acceleration engine based on RISC-V
by: Zhang Xiaolei, et al.
Published: (2023-02-01)

Hardware Software Co-Design for Multi-Threaded Computation on RISC-V-Based Multicore System
by: Binh Kieu-do-Nguyen, et al.
Published: (2024-01-01)

P-CORE: Exploring RISC-V Packed-SIMD Extension for CNNs
by: Muhammad Ali, et al.
Published: (2025-01-01)

Towards a Modular RISC-V Based Many-Core Architecture for FPGA Accelerators
by: Ahmed Kamaleldin, et al.
Published: (2020-01-01)

Real-Time RISC-V-Based CAN-FD Bus Diagnosis Tool
by: Cosmin-Andrei Popovici, et al.
Published: (2023-01-01)

A Custom RISC-V Based SOC Chip for Commodity Barcode Identification
by: Sijie Lin, et al.
Published: (2024-01-01)

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor
by: Idris O. Somoye, et al.
Published: (2024-04-01)

FPGA Prototyping of Heterogeneous Security Architecture for Educational Purposes
by: Stefan Stoyanov, et al.
Published: (2025-07-01)

System Verification and FPGA Implementation of Hardware Preemptive Scheduler for RISC-V Processor
by: Ionel Zagan, et al.
Published: (2025-01-01)

FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption
by: Ashwaq Talib Hashim, et al.
Published: (2010-04-01)

NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V
by: Hakan Uzuner, et al.
Published: (2024-02-01)

A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System
by: Haifeng Zhang, et al.
Published: (2021-09-01)

Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency
by: Zhiwei Jin, et al.
Published: (2025-01-01)

Research and Design of Embedded RISC-V Out-of-Order Execution Processor
by: LI Yuqian, JIAO Jiye, LIU Youyao, HAO Zhenhe
Published: (2021-02-01)

Efficient Prefetch and Issue Scheduling Approaches for Simultaneous Multithreading Applied to Superscalar RISC-V Processor
by: Hananya Ribo, et al.
Published: (2025-01-01)

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms
by: Görkem Nişancı, et al.
Published: (2022-08-01)

Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation
by: Ionel Zagan, et al.
Published: (2023-01-01)