Designing a Novel high-speed ternary-logic multiplier using GNRFET Technology
Abstract:This paper presents a novel design of a ternary multiplierbased on graphene nanoribbon field-effect transistor(GNRFET). GNRFET, as a new material with superiorphysical and electronic properties, can be a good choiceinstead of conventional devices such as metal–oxide–semiconductor field-effe...
| Published in: | Journal of Optoelectronical Nanostructures |
|---|---|
| Main Authors: | Zahra Rohani, Azadeh Alsadat Emrani Zarandi |
| Format: | Article |
| Language: | English |
| Published: |
Islamic Azad University, Marvdasht Branch
2023-01-01
|
| Subjects: | |
| Online Access: | https://jopn.marvdasht.iau.ir/article_5800_0625b6798dc77919fd9edce5919f3dbc.pdf |
Similar Items
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells
by: Arezoo Dabaghi Zarandi, et al.
Published: (2020-01-01)
by: Arezoo Dabaghi Zarandi, et al.
Published: (2020-01-01)
New ternary decoders using hybrid memristor-MOS logic
by: Ramesh Kumar, et al.
Published: (2025-06-01)
by: Ramesh Kumar, et al.
Published: (2025-06-01)
High-speed and power-efficient ternary logic designs using GNR transistors
by: Kuruva Mahesh, et al.
Published: (2024-03-01)
by: Kuruva Mahesh, et al.
Published: (2024-03-01)
Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders
by: C. Venkataiah, et al.
Published: (2023-01-01)
by: C. Venkataiah, et al.
Published: (2023-01-01)
Design of Ternary Logic and Arithmetic Circuits Using GNRFET
by: Zarin Tasnim Sandhie, et al.
Published: (2020-01-01)
by: Zarin Tasnim Sandhie, et al.
Published: (2020-01-01)
Ternary Full Adder Designs Employing Unary Operators and Ternary Multiplexers
by: Ramzi A. Jaber, et al.
Published: (2023-05-01)
by: Ramzi A. Jaber, et al.
Published: (2023-05-01)
Performance analysis of 4-bit ternary adder and multiplier using CNTFET for high speed arithmetic circuits
by: C. Venkataiah, et al.
Published: (2023-01-01)
by: C. Venkataiah, et al.
Published: (2023-01-01)
Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
by: Katyayani Chauhan, et al.
Published: (2025-03-01)
by: Katyayani Chauhan, et al.
Published: (2025-03-01)
Performance evaluation and optimization of triple cascode operational transconductance amplifiers using GNRFET technology for low power smart devices
by: Faraz Hashmi, et al.
Published: (2025-01-01)
by: Faraz Hashmi, et al.
Published: (2025-01-01)
Analog models for ternary combinational logic elements
by: Semenov, Andrey Andreevich, et al.
Published: (2024-12-01)
by: Semenov, Andrey Andreevich, et al.
Published: (2024-12-01)
Ternary Logic Design Based on Novel Tunneling-Drift-Diffusion Field-Effect Transistors
by: Bin Lu, et al.
Published: (2025-08-01)
by: Bin Lu, et al.
Published: (2025-08-01)
Carbon Nanotube and Resistive Random Access Memory Based Unbalanced Ternary Logic Gates and Basic Arithmetic Circuits
by: Furqan Zahoor, et al.
Published: (2020-01-01)
by: Furqan Zahoor, et al.
Published: (2020-01-01)
Energy-efficient design of CNTFET-based quaternary arithmetic circuits
by: Ajay Rupani, et al.
Published: (2025-08-01)
by: Ajay Rupani, et al.
Published: (2025-08-01)
Swarm intelligence versus direct cover algorithms in synthesis of Multi-Valued Logic functions
by: Mostafa Abd-El-Barr, et al.
Published: (2024-01-01)
by: Mostafa Abd-El-Barr, et al.
Published: (2024-01-01)
Design and Application of Memristive Balanced Ternary Univariate Logic Circuit
by: Xiaoyuan Wang, et al.
Published: (2023-09-01)
by: Xiaoyuan Wang, et al.
Published: (2023-09-01)
Ternary Arithmetic Logic Unit Design Utilizing Carbon Nanotube Field Effect Transistor (CNTFET) and Resistive Random Access Memory (RRAM)
by: Furqan Zahoor, et al.
Published: (2021-10-01)
by: Furqan Zahoor, et al.
Published: (2021-10-01)
Developed ternary processor units based on analog models of ternary logic elements
by: Semenov, Andrey Andreevich, et al.
Published: (2025-06-01)
by: Semenov, Andrey Andreevich, et al.
Published: (2025-06-01)
High speed multiplier design using Decomposition Logic
by: Ramanathan Palaniappan, et al.
Published: (2009-01-01)
by: Ramanathan Palaniappan, et al.
Published: (2009-01-01)
Low power area efficient self-gated flip flop: Design, implementation and analysis in emerging devices
by: Owais Ahmad Shah, et al.
Published: (2022-11-01)
by: Owais Ahmad Shah, et al.
Published: (2022-11-01)
CNTFET-based digital arithmetic circuit designs in ternary logic with improved performance
by: Namineni Gireesh, et al.
Published: (2024-03-01)
by: Namineni Gireesh, et al.
Published: (2024-03-01)
Performance evaluation of high speed compressors for high speed multipliers
by: Nirlakalla Ravi, et al.
Published: (2011-01-01)
by: Nirlakalla Ravi, et al.
Published: (2011-01-01)
Stability and Hyperstability of Ternary Hom-Multiplier on Ternary Banach Algebra
by: Vahid Keshavarz, et al.
Published: (2025-06-01)
by: Vahid Keshavarz, et al.
Published: (2025-06-01)
Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication
by: Hemanth Krishna L., et al.
Published: (2021-01-01)
by: Hemanth Krishna L., et al.
Published: (2021-01-01)
Two Efficient Ternary Adder Designs Based On CNFET Technology
by: Masoud Mahjoubi, et al.
Published: (2021-06-01)
by: Masoud Mahjoubi, et al.
Published: (2021-06-01)
Performance evaluation of SRAM design using different field effect transistors
by: C. Venkataiah, et al.
Published: (2023-01-01)
by: C. Venkataiah, et al.
Published: (2023-01-01)
Design of n-Bit Adder without Applying Binary to Quaternary Conversion
by: Walaa Khalaf, et al.
Published: (2019-03-01)
by: Walaa Khalaf, et al.
Published: (2019-03-01)
Design of SRAM with CNFET based on ternary literal circuit
by: Kang Yaopeng, et al.
Published: (2018-03-01)
by: Kang Yaopeng, et al.
Published: (2018-03-01)
Design and implementation of FinFET and GnrFET based nano arithmetic logic unit
by: Samanthapudi Swathi, et al.
Published: (2025-09-01)
by: Samanthapudi Swathi, et al.
Published: (2025-09-01)
Novel Ternary Logic Gates Design in Nanoelectronics
by: Sajjad Etezadi, et al.
Published: (2019-01-01)
by: Sajjad Etezadi, et al.
Published: (2019-01-01)
An RTL-Based General Synthesis Methodology for Device-Independent Ternary Logic Circuits
by: Hanmok Park, et al.
Published: (2025-01-01)
by: Hanmok Park, et al.
Published: (2025-01-01)
Ternary Toward Binary: Circuit-Level Implementation of Ternary Logic Using Depletion-Mode and Conventional MOSFETs
by: Hyundong Lee, et al.
Published: (2025-01-01)
by: Hyundong Lee, et al.
Published: (2025-01-01)
Reliably In‐Memory Ternary Stateful Logic Computing Based on Tri‐State Memristors with High On/Off Ratio
by: Junqi You, et al.
Published: (2025-09-01)
by: Junqi You, et al.
Published: (2025-09-01)
DESIGN AND PERFORMANCE ANALYSIS OF TERNARY LOGIC BASED ALU USING DOUBLE PRECISION FLOATING POINT
by: Nagarathna R, et al.
Published: (2024-09-01)
by: Nagarathna R, et al.
Published: (2024-09-01)
A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator
by: Naveen Kr. Kabra, et al.
Published: (2021-01-01)
by: Naveen Kr. Kabra, et al.
Published: (2021-01-01)
Comprehensive survey of ternary full adders: Statistics, corrections, and assessments
by: Sarina Nemati, et al.
Published: (2023-05-01)
by: Sarina Nemati, et al.
Published: (2023-05-01)
Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
by: Geetam Singh Tomar, et al.
Published: (2021-08-01)
by: Geetam Singh Tomar, et al.
Published: (2021-08-01)
Ternary encoder and decoder designs in RRAM and CNTFET technologies
by: Shams Ul Haq, et al.
Published: (2024-03-01)
by: Shams Ul Haq, et al.
Published: (2024-03-01)
Non-Iterative, Unique, and Logical Formula-Based Technique to Determine Maximum Load Multiplier and Practical Load Multiplier for Both Transmission and Distribution Systems
by: Sharmistha Nandi, et al.
Published: (2023-06-01)
by: Sharmistha Nandi, et al.
Published: (2023-06-01)
Ternary computing using a novel spintronic multi-operator logic-in-memory architecture
by: Amirhossein Fathollahi, et al.
Published: (2025-03-01)
by: Amirhossein Fathollahi, et al.
Published: (2025-03-01)
Ternary combinational logic gate design based on tri-valued memristors
by: Xiao-Jing Li, et al.
Published: (2023-10-01)
by: Xiao-Jing Li, et al.
Published: (2023-10-01)
Similar Items
-
A Systematic Method to Design Efficient Ternary High Performance CNTFET-Based Logic Cells
by: Arezoo Dabaghi Zarandi, et al.
Published: (2020-01-01) -
New ternary decoders using hybrid memristor-MOS logic
by: Ramesh Kumar, et al.
Published: (2025-06-01) -
High-speed and power-efficient ternary logic designs using GNR transistors
by: Kuruva Mahesh, et al.
Published: (2024-03-01) -
Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders
by: C. Venkataiah, et al.
Published: (2023-01-01) -
Design of Ternary Logic and Arithmetic Circuits Using GNRFET
by: Zarin Tasnim Sandhie, et al.
Published: (2020-01-01)
