A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS
In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a...
| الحاوية / القاعدة: | Jordanian Journal of Computers and Information Technology |
|---|---|
| المؤلفون الرئيسيون: | , , |
| التنسيق: | مقال |
| اللغة: | الإنجليزية |
| منشور في: |
Scientific Research Support Fund of Jordan (SRSF) and Princess Sumaya University for Technology (PSUT)
2019-08-01
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| الموضوعات: | |
| الوصول للمادة أونلاين: | http://jjcit.org/Volume%2005,%20Number%2002/8-DOI%2010.5455-jjcit.71-1556375171.pdf |
| _version_ | 1857032198222249984 |
|---|---|
| author | Jamil Al-Azzeh Mohammed Agmal Igor Zotov |
| author_facet | Jamil Al-Azzeh Mohammed Agmal Igor Zotov |
| author_sort | Jamil Al-Azzeh |
| collection | DOAJ |
| container_title | Jordanian Journal of Computers and Information Technology |
| description | In this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a set of independently routed w-bit-wide flits. The device achieves at least 78% throughput for uniformly distributed traffic and an asymptot-ic higher bound of 100%. In contrast to the state-of-the-art VOQ-based switch architectures, the proposed switch is shown to reach its maximum throughput with no internal speedup required and has an order of mag-nitude lower hardware complexity. Compared to existing buffered crossbar non-VOQ switches with typical flit scheduling mechanisms, the proposed device demonstrates slightly higher throughput and substantially short-er delays in some practically important cases. |
| format | Article |
| id | doaj-art-b65d7cbdc2d54f3293d4e7750bb2aa3e |
| institution | Directory of Open Access Journals |
| issn | 2413-9351 2415-1076 |
| language | English |
| publishDate | 2019-08-01 |
| publisher | Scientific Research Support Fund of Jordan (SRSF) and Princess Sumaya University for Technology (PSUT) |
| record_format | Article |
| spelling | doaj-art-b65d7cbdc2d54f3293d4e7750bb2aa3e2025-08-19T19:39:49ZengScientific Research Support Fund of Jordan (SRSF) and Princess Sumaya University for Technology (PSUT)Jordanian Journal of Computers and Information Technology2413-93512415-10762019-08-0105214616210.5455/jjcit.71-1556375171A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITSJamil Al-AzzehMohammed AgmalIgor ZotovIn this paper, a packet switch architecture for mesh-connected multiprocessors based on the use of a set of in-put FIFO buffers and an output register matrix controlled by a novel distributed timing-based scheduling scheme is proposed. Simple static routing is assumed, with each packet split into a set of independently routed w-bit-wide flits. The device achieves at least 78% throughput for uniformly distributed traffic and an asymptot-ic higher bound of 100%. In contrast to the state-of-the-art VOQ-based switch architectures, the proposed switch is shown to reach its maximum throughput with no internal speedup required and has an order of mag-nitude lower hardware complexity. Compared to existing buffered crossbar non-VOQ switches with typical flit scheduling mechanisms, the proposed device demonstrates slightly higher throughput and substantially short-er delays in some practically important cases.http://jjcit.org/Volume%2005,%20Number%2002/8-DOI%2010.5455-jjcit.71-1556375171.pdfMultiprocessorMesh topologyPacket switchingInput-queued switchFIFO-bufferFlitPipeliningThroughput |
| spellingShingle | Jamil Al-Azzeh Mohammed Agmal Igor Zotov A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS Multiprocessor Mesh topology Packet switching Input-queued switch FIFO-buffer Flit Pipelining Throughput |
| title | A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS |
| title_full | A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS |
| title_fullStr | A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS |
| title_full_unstemmed | A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS |
| title_short | A PARALLEL PIPELINED PACKET SWITCH ARCHITECTURE FOR MESH-CONNECTED MULTIPROCESSORS WITH INDEPENDENTLY ROUTED FLITS |
| title_sort | parallel pipelined packet switch architecture for mesh connected multiprocessors with independently routed flits |
| topic | Multiprocessor Mesh topology Packet switching Input-queued switch FIFO-buffer Flit Pipelining Throughput |
| url | http://jjcit.org/Volume%2005,%20Number%2002/8-DOI%2010.5455-jjcit.71-1556375171.pdf |
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