Efficient design of 15:4 counter using a novel 5:3 counter for high‐speed multiplication

• Published in: IET Computers & Digital Techniques
• Main Authors: Hemanth Krishna L., Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, Noor Mahammad S
• Format: Article
• Language: English
• Published: Wiley 2021-01-01
• Subjects: counting circuits; logic design; multiplying circuits
• Online Access: https://doi.org/10.1049/cdt2.12002
• ISSN: 1751-8601; 1751-861X

Abstract This paper proposes an efficient approach to design high‐speed, accurate multipliers. The proposed multiplier design uses the proposed efficient 15:4 counter for the partial product reduction stage. This proposed 15:4 counter is designed using a novel 5:3 counter. The proposed 5:3 counter uses input re‐ordering circuitry at the input side. As a result, the number of output combinations can be reduced to 18 from 32. As a result, the circuit complexity reduces. The proposed 5:3 counter and 15:4 counter are on an average 28% and 19% improvement in the power delay product compared with the existing designs. The 16‐bit multiplier designed using 5:3 and 15:4 counters is an average 22.5% improvement in power delay product compared with the existing designs.