NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory

In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neur...

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Bibliographic Details
Published in:IEEE Journal of the Electron Devices Society
Main Authors: Jung Nam Kim, Jaehong Lee, Jo Eun Kim, Suck Won Hong, Minsuk Koo, Yoon Kim
Format: Article
Language:English
Published: IEEE 2022-01-01
Subjects:
3-D stacked synapse array
neuromorphic system
artificial neural network
synapse array
synapse device
CTF memory
Online Access:https://ieeexplore.ieee.org/document/9899406/

Internet

https://ieeexplore.ieee.org/document/9899406/

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