Jayakrishnan, M., Chang, A., & Kim, T. T. (2018, March). Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications. Journal of Low Power Electronics and Applications.
Chicago Style (17th ed.) CitationJayakrishnan, Mini, Alan Chang, and Tony Tae-Hyoung Kim. "Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications." Journal of Low Power Electronics and Applications Mar. 2018.
MLA (9th ed.) CitationJayakrishnan, Mini, et al. "Opportunistic Design Margining for Area and Power Efficient Processor Pipelines in Real Time Applications." Journal of Low Power Electronics and Applications, Mar. 2018.
Warning: These citations may not always be 100% accurate.