Evaluating a number of cache coherency misses based on a statistical model
False cache sharing happens when different parallel execution threads update the variables that reside in the same cache line. We suggest in this paper to evaluate the number of cache misses using code instrumentation and post-mortem trace analysis: the probability of the false sharing cache miss (d...
| 出版年: | Труды Института системного программирования РАН |
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| 第一著者: | |
| フォーマット: | 論文 |
| 言語: | 英語 |
| 出版事項: |
Russian Academy of Sciences, Ivannikov Institute for System Programming
2018-10-01
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| 主題: | |
| オンライン･アクセス: | https://ispranproceedings.elpub.ru/jour/article/view/597 |
| 要約: | False cache sharing happens when different parallel execution threads update the variables that reside in the same cache line. We suggest in this paper to evaluate the number of cache misses using code instrumentation and post-mortem trace analysis: the probability of the false sharing cache miss (defined as a memory write issued by one thread between two consecutive memory accesses issued by another thread) is calculated based on the gathered event trace, where each event is a memory access with a timestamp. The tracer tool is implemented as a GCC compiler pass, whereas the post-mortem analyzer is a separate application that gets the trace collection gathered on a sample application input data as its own input. Program slowdown in our approach is ~10 times, and it is dependent on a sampling probability but it does not depend on a cache line size. |
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| ISSN: | 2079-8156 2220-6426 |