Search Results - HARDWARE ACCELERATION

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    Hardware for Deep Learning Acceleration by Choongseok Song, ChangMin Ye, Yonguk Sim, Doo Seok Jeong

    Published in Advanced Intelligent Systems (2024-10-01)
    “…To cope with the consequent prohibitive latency for computation, 1) general‐purpose hardware, e.g., central processing units and graphics processing units, has been redesigned, and 2) various DL accelerators have been newly introduced, e.g., neural processing units, and computing‐in‐memory units for deep NN‐based DL, and neuromorphic processors for spiking NN‐based DL. …”
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    Hardware Accelerated Sequence Alignment with Traceback by Scott Lloyd, Quinn O. Snell

    “…A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. …”
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    Hardware accelerators for processing clusters in binary vectors by Skliarova Iouliia, Skliarov Valeri

    Published in ITM Web of Conferences (2024-01-01)
    “…The paper suggests fast hardware accelerators for discovering clusters of zeros and/or ones in binary vectors. …”
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    On-Chip Reconfigurable Hardware Accelerators for Popcount Computations by Valery Sklyarov, Iouliia Skliarova, João Silva

    “…The paper suggests two types of hardware accelerators that are (1) designed in FPGAs and (2) implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. …”
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    A Component-Centric Perspective on Hardware Accelerators for LLMs by Jia Ke, Wang Xiaohao, Chen Hailin, Zhong Wei, Li Xinxiong, Fang Zenan, An Fengwei

    Published in IEEE Access (2025-01-01)
    “…The rapid scaling of large language models (LLMs), especially those based on the Transformer architecture, has intensified the demand for high-performance hardware accelerators capable of supporting massive parameter counts with minimal latency and energy consumption. …”
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    Hardware Acceleration of Number Theoretic Transform in zk-SNARK by ZHAO Haixu, CHAI Zhilei, HUA Pengcheng, WANG Feng, DING Dong

    Published in Jisuanji kexue yu tansuo (2024-02-01)
    Subjects: “…field programmable gate array (fpga); zero-knowledge succinct non-interactive arguments of knowledge (zk-snark); modular multiplication; number theoretic transform; hardware acceleration…”
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    A Flexible Hardware Accelerator for Booth Polynomial Multiplier by Omar S. Sonbul

    Published in Applied Sciences (2024-04-01)
    “…This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. …”
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    Quick Boot of Trusted Execution Environment With Hardware Accelerators by Trong-Thuc Hoang, Ckristian Duran, Duc-Thinh Nguyen-Hoang, Duc-Hung Le, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham

    Published in IEEE Access (2020-01-01)
    “…In this paper, a RISC-V system compatible with TEEs featuring security algorithm accelerators is presented. The hardware accelerators are the SHA-3 hash and the Ed25519 elliptic curve algorithms. …”
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    Efficient Hardware Architectures for Accelerating Deep Neural Networks: Survey by Pudi Dhilleswararao, Srinivas Boppu, M. Sabarimalai Manikandan, Linga Reddy Cenkeramaddi

    Published in IEEE Access (2022-01-01)
    “…This review article is intended to guide hardware architects to accelerate and improve the effectiveness of deep learning research.…”
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