Search Results - INSTRUCTION SET ARCHITECTURE

General Architecture and Instruction Set Enhancements for Multimedia Applications by Mansour Assaf, Aparna Rajesh

Subjects: “…Instruction Set Architecture (ISA)…”
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Function-call Instruction Characteristic Analysis Based Instruction Set Architecture Recognization Method for Firmwares by JIA Fan, YIN Xiaokang, GAI Xianzhe, CAI Ruijie, LIU Shengli

Subjects: “…instruction set architecture|classification techniques|reverse analysis engineering|embedded device security|static analysis…”
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PISA-DMA: Processing-in-Memory Instruction Set Architecture Using DMA by Won Jun Lee, Chang Hyun Kim, Yoonah Paik, Seon Wook Kim

Subjects: “…instruction set architecture…”
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IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions by Yuze Wang, Peng Liu, Yingtao Jiang

“…To address this problem that may cause potentially serious security breaches, the instruction set architecture (ISA) monitor and secure cache (IMSC) is proposed. …”
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Simplified Instruction Set Architecture Accelerates Chip Development and Wins the 2022 Draper Prize by Chris Palmer

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The Task of Automatic Generation of Peephole-Optimizations: Approaches Overview, Solution of the Optimal Expansion of Managed Instructions Set Architecture by Anna Antipina

Subjects: “…instruction set architecture…”
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Addressing Mode Extension to the ARM/Thumb Architecture by KIM, D.-H.

Subjects: “…instruction set design…”
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Special Instruction Set Processor for Convolutional Neural Network Based on RISC-V by LIAO Hansong, WU Zhaohui, LI Bin

Subjects: “…risc-v instruction set|convolutional neural network(cnn)|domain specific architecture(dsa)|special instruction set processor|hardware acceleration…”
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Comprehensive Review of Research on Dynamic Binary Translation Techniques by ZHANG Jin, SHAN Zehu, LIU Xiaodong, WANG Wenzhu, YU Jie, PENG Long, XIE Qiyou

Subjects: “…dynamic binary translation; instruction set architecture; instruction translation; software compatibility…”
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Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation by Ionel Zagan, Vasile Gheorghiţă Găitan

“…This artcle presents field-programmable gate array (FPGA) soft-core processors integration based on different instruction set architectures (ISA), custom central processing unit (CPU) datapath, dedicated hardware thread context, and hardware real-time operating system (RTOS) implementations. …”
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Open-source chip,RISC-V and agile development by Huizhe WANG, Dan TANG, Zihao YU, Zhigang LIU, Biwei XIE, Yungang BAO

Subjects: “…open-source chip;agile development;computer architecture;instruction set architecture…”
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Designing RISC-V Instruction Set Extensions for Artificial Neural Networks: An LLVM Compiler-Driven Perspective by Karthikeyan Kalyanasundaram Balasubramanian, Mirco Di Salvo, Walter Rocchia, Sergio Decherchi, Marco Crepaldi

Subjects: “…instruction set architecture…”
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Design modified architecture for MCS-51 with innovated instructions based on VHDL by Abd-Elmoneim Mohamed Fouda, Assem Badr Eldeen

“…For the MCS-51 family, utilizing a reserved bit, and the unused machine code “A5h” we can modify the conventional instruction set architecture (ISA) and develop two macro instructions for data manipulation. …”
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A Transdisciplinary Approach to Differentiated Instruction by Russell Jay Hendel

Subjects: “…goal setting…”
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Advancements in Microprocessor Architecture for Ubiquitous AI—An Overview on History, Evolution, and Upcoming Challenges in AI Implementation by Fatima Hameed Khan, Muhammad Adeel Pasha, Shahid Masud

Subjects: “…instruction set architecture…”
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SIMULATION OF PERIPHERAL DEVICE SECURITY: IMPLEMENTATION AND PRACTICAL EVLUATION OF ADDRESS SPACES PROTECTION IN A TRUSTED MICROPROCESSOR EMULATOR by Mikael A. Kondakhchan, Nikita A. Grevtsev, Peter A. Chibisov

Subjects: “…iommu, instruction set simulator, architectural modeling, pagewalk, countering cyber threats.…”
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Bratter: An Instruction Set Extension for Forward Control-Flow Integrity in RISC-V by Seonghwan Park, Dongwook Kang, Jeonghwan Kang, Donghyun Kwon

“…In recent decades, there has been an increasing number of studies on control flow integrity (CFI), particularly those implementing hardware-assisted CFI solutions that utilize a special instruction set extension. More recently, ARM and Intel, which are prominent processor architectures, also announced instruction set extensions for CFI called branch target identification (BTI) and control-flow enhancement technology (CET), respectively. …”
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Reconfigurable and Scalable Artificial Intelligence Acceleration Hardware Architecture With RISC-V CNN Coprocessor for Real-Time Seizure Detection by Shuenn-Yuh Lee, Ming-Yueh Ku, Sing-Yu Pan, Chou-Ching Lin

“…This study also proposes an artificial intelligence acceleration (AIA) hardware architecture, including a deep learning accelerator (DLA) and a two-stage reduced instruction set computer-V (RISC-V) central control unit (CPU), to implement the detection algorithm in real-time operation. …”
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HW-CDI: Hard-Wired Control Data Integrity by Yongsuk Lee, Gyungho Lee

Subjects: “…instruction set architecture…”
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On the Feasibility and Limitations of Just-in-Time Instruction Set Extension for FPGA-Based Reconfigurable Processors by Mariusz Grad, Christian Plessl

“…Reconfigurable instruction set processors provide the possibility of tailor the instruction set of a CPU to a particular application. …”
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