Search Results - OPERAND SCHEDULING

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  1. 1

    Optimizing the allocation of technological resources of an air transport system in the presence of a schedule and fuzzy input data by V. A. Romanenko

    “…The problem of optimal allocation of technological resources (operators) of a technical or organizational-technical system, designed to serve certain objects (operands) according to a given schedule, is considered. …”
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  2. 2

    COMPARISON OF INSTRUCTION SCHEDULING AND REGISTER ALLOCATION FOR MIPS AND HPL-PD ARCHITECTURE FOR EXPLOITATION OF INSTRUCTION LEVEL PARALLELISM by Rajendra Kumar

    Published in Engineering Heritage Journal (2018-01-01)
    “…The integrated approaches for instruction scheduling and register allocation have been promising area of research for code generation and compiler optimization. …”
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  3. 3

    Research on <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub></math></in... by Zhanpeng JIANG, Mingwei SUN, Hai HUANG, Jiang XU, Zhiwei LIU, Rui BAI, Zhou FANG, Jiaxing QU

    Published in Tongxin xuebao (2022-02-01)
    “…A quadratic extended-domain finely integrated operand scanning (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math></inline-formula>-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm, the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature, the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time, clock frequency and the area-time product, and also has certain advantages in the overall Optimal ate pair implementation.…”
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  4. 4

    Research on <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub></math></in... by Zhanpeng JIANG, Mingwei SUN, Hai HUANG, Jiang XU, Zhiwei LIU, Rui BAI, Zhou FANG, Jiaxing QU

    Published in Tongxin xuebao (2022-02-01)
    “…A quadratic extended-domain finely integrated operand scanning (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math></inline-formula>-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm, the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature, the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time, clock frequency and the area-time product, and also has certain advantages in the overall Optimal ate pair implementation.…”
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    Article


  5. 5

    Implementation of Loop Pipelining and Assignment Inlining in the C-to-HDL Translator by Alexey Merkulov, Andrey Belevantsev

    “…Finally, software pipelining following the usual modulo scheduling scheme is also performed with the same resource constraint limit relaxations as described for instruction scheduling.Experimental results demonstrate that these optimizations significantly improve (up to 4x) the performance of generated code.…”
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  6. 6

    Combining different types of binary operations in the nonposition calculators by Valeriy Petrovich Irhin, Vyacheslav Aleksandrovich Melnik, Dmitriy Sergeevich Shvedov

    “…At the end of the work is scheduled path to overcome it.…”
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