Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms

Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms

According to Moore's law, Integrated Chips (IC) doubles its capacity every 18 months. This causes an exponential increase of the available area, and hence,the complexity of modern digital designs. This consistent enormous gross challenges different research areas in Electronic Design Automation...

Full description

Bibliographic Details
Main Author: Elbayoumi, Mahmoud Atef Mahmoud Sayed
Other Authors: Electrical and Computer Engineering
Format: Others
Published: Virginia Tech 2015
Subjects:
Verification
logic synthesis
SAT
BDDs
Low power
timing aware
Online Access:http://hdl.handle.net/10919/51221

Internet

http://hdl.handle.net/10919/51221

Similar Items