Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs

Effects of gate stack structural and process defectivity on high- k dielectric dependence of nbti reliability in 32 nm technology node PMOSFETs

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We present a simulation study on negative bias temperature instability (NBTI) induced hole trapping in E ′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high- k PMOSFET gate stacks using the two-stage NBTI model. The resulting degrada...

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Bibliographic Details
Main Authors: Abdul Wahab, Y. (Author), Bukhori, M.F (Author), Hussin, H. (Author), Soin, N. (Author), Wan Muhamad Hatta, S. (Author)
Format: Article
Language:English
Published: Hindawi Publishing Corporation 2014
Subjects:
Article
degradation
density
dipole
electric field
electric potential
electrical parameters
field effect transistor
geometry
hafnium
hydrodynamics
mathematical model
negative bias temperature instability
relaxation time
reliability
silicon dioxide
temperature stress
thickness
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