Showing 1 - 20 results of 24 for search 'PROCESS DESIGN', query time: 2.05s Refine Results
  1. 1
    by Ping-Chen Huang, 黃品甄
    Published 2006
    ... to investigate the high frequency behaviors of negative resistance cells when designing MMW CMOS VCOs. Several...
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  2. 2
    by Shih-Kai Lin, 林士凱
    Published 2010
    ... introduced a 71-76 GHz balanced resistive gate-pumped mixer using in pHEMT process. Based on this topology, a...
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  3. 3
    by Yi-Hsien Cho, 卓宜賢
    Published 2005
    .... Therefore, to design a high frequency oscillator with low phase noise is important. The goal of the thesis...
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  4. 4
    by Shih-Fong Chao, 趙世峰
    Published 2007
    ... to those in GaAs HEMT process. The second part of the dissertation presents a new method to design band...
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  5. 5
    by Kuang-Sheng Yeh, 葉光聖
    Published 2016
    ... are minimized. The first BDA is realized in 90-nm CMOS process. From 57 to 66 GHz, in receiving mode, the gain...
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  6. 6
    by Jun-Kai Wang, 王俊凱
    Published 2017
    ...碩士 === 國立臺灣大學 === 電信工程學研究所 === 105 === This thesis demonstrates the design and measurement results...
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  7. 7
    by Chieh-An Lin, 林介安
    Published 2009
    ... with wide tuning range and low phase noise is implemented in CMOS 0.18 μm process. By using the new...
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  8. 8
    by Jung-Hau Chen, 陳仲豪
    Published 2010
    ... parts. The first part introduced a 15-50 GHz doubly balanced resistive ring mixer using CMOS process...
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  9. 9
    by Tzu-Yuan Huang, 黃梓原
    Published 2015
    ...) in 0.18-μm CMOS and comparable performance with the DAs in advanced process. The third part is a power...
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  10. 10
    by Cheng-Yu Chen, 陳政宇
    Published 2017
    ... phase variation and high gain control range VGA using 65-nm CMOS process is applied on a 38 GHz phased...
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  11. 11
    by Ping Chen, 陳平
    Published 2010
    ... process. The second amplifier is a distributed amplifier using high-pass transmission lines, and its...
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  12. 12
    by Chieh-Min Lo, 羅玠旻
    Published 2005
    ...) are designed, and implemented using CMOS process. LNA is the critical component in the RF front-end circuits...
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  13. 13
    by Jeffrey Lee, 李杰穎
    Published 2008
    ...), is proposed. In order to implement this idea, first we design and measure a single-pole-single-throw (SPST...
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  14. 14
    by To-Po Wang, 王多柏
    Published 2007
    ... was fabricated in a low-cost process while demonstrating the low phase noise. This chip is also the first 0.35-μm...
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  15. 15
    by Shih-Chieh Shin, 忻士傑
    Published 2005
    ... on the same die, thereby reducing the production cost. However, compared to GaAs processes, the inherent...
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  16. 16
    by Bo-Yu Chen, 陳柏羽
    Published 2015
    ... high gain low noise amplifier in WIN 0.1-μm process for radio astronomy application. The measurement...
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  17. 17
    by Bo-Jr Huang, 黃柏智
    Published 2010
    ...博士 === 臺灣大學 === 電信工程學研究所 === 98 === In this dissertation, the designs and analysis of RF...
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  18. 18
    by Hsin-Chiang Liao, 廖信強
    Published 2012
    ... in TSMC 90-nm CMOS process. In order to improve the I/Q mismatch in the design of quadrature phase, a co...
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  19. 19
    by Wei-Cheng Huang, 黃煒程
    Published 2018
    ...碩士 === 國立臺灣大學 === 電信工程學研究所 === 107 === This thesis presents the design and measurement results of a...
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  20. 20
    by Pin-Cheng Huang, 黃品澄
    Published 2011
    ... broadband power amplifier using 0.18-μm CMOS process. The physical limitations for designing the transformer...
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