Showing 1 - 20 results of 39 for search 'PROCESS DESIGN', query time: 1.14s Refine Results
  1. 1
    by Jiun-Lin Tsay, 蔡俊琳
    Published 1994
    ... and BiCMOS process.e performances have been measured. The relations between differ...
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  2. 2
    by Jin-Cheng Huang, 黃金城
    Published 1995
    ... designed and fabricated in a 0.8um CMOS process, is presented. The A/D...
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  3. 3
    by Hua-Shan Hu, 胡華珊
    Published 2003
    ... with the new compensation circuit is designed to 160 MHz. In CMOS process, the most suitable photodiode which...
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  4. 4
    by Chien-Ming Shih, 施建名
    Published 2008
    ... and used in all kinds of circuits extensively. Developing the OPAMPs automatic design can speed up...
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  5. 5
    by Gwo-Ming Chen, 陳國明
    Published 1993
    ...碩士 === 國立交通大學 === 電子研究所 === 81 === In this thesis, two fully CMOS process compatible...
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  6. 6
    by Yu-Yee Liow, 廖以義
    Published 0
    ... in the design of high-speed analog-to-digital converters. In this thesis, new architectures for high-speed CMOS...
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  7. 7
    by Shu-Yuan Chin, 秦旭沅
    Published 1995
    ...博士 === 國立交通大學 === 電子研究所 === 83 === This thesis describes the design of high-performance data...
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  8. 8
    by Yon-Chun Shie, 徐永傳
    Published 1994
    ... of problem. Two chips are designed in this thesis to realize parallel processing of image...
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  9. 9
    by Chia-Hung Tsen, 岑嘉宏
    Published 2003
    .... These two proposed chips are fabricated in a standard 0.25um single-poly-five-metal (1P5M) CMOS process...
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  10. 10
    by Sheng-Hao Chen, 陳勝豪
    Published 2003
    ... of the parasitic lateral bipolar junction transistor in the CMOS process. Based on the device physic properties...
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  11. 11
    by Wei-Haur Jan, 詹瑋豪
    Published 1995
    ... with two different structures have been designed and fabricated by modified 0.8(m double...
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  12. 12
    by Wei-Tzung Liu, 劉衛宗
    Published 2006
    ...碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 94 === In this thesis , the design of Indirect Transfer Wave...
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  13. 13
    by Chiu-Hung Cheng, 鄭秋宏
    Published 2003
    ... structure with ratio memory and the cellular nonlinear(neural) network universal machine are designed...
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  14. 14
    by Jui-Chien Liu, 劉瑞謙
    Published 1994
    .... The structure can be designed without the need for the operational amplifiers with either high...
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  15. 15
    by Liang-Hung Lu, 呂良鴻
    Published 1993
    ... and current minimum-maximum circuit for analogignal processing and analog computing...
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  16. 16
    by Yu-Chuan Shih, 施育全
    Published 2004
    ... cells fabricated in a 0.35 �慆 single-poly-triple-metal (1P3M) N-well CMOS process are designed by using...
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  17. 17
    by Chung-Yun Chou, 周忠昀
    Published 2005
    ...博士 === 國立交通大學 === 電子工程系所 === 93 === In this thesis, the design methodologies and implementation...
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  18. 18
    by Chang-Ching Tu, 杜長慶
    Published 2004
    ... amino groups on the particle surface are assembled onto Au NPs. Theoretically, the assembly process can...
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  19. 19
    by Hsun-Hsiu Huang, 黃煦修
    Published 2001
    ... for strengthening the transmit power. A self-bias circuit is designed here to compensate the technique process...
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  20. 20
    by Jui-Lin Lai, 賴瑞麟
    Published 2004
    ... are designed and analyzed. The thesis is consist of three main parts: (1) the analysis and design...
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