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1by Cheng-Tsung Lin, 林正宗“...碩士 === 國立臺灣科技大學 === 電子工程系 === 98 === This thesis presents the analysis and design of a high...”
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2“... or industrial areas. Due to the improvement of IC process for the past few years, the size and power consumption...”
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3“... application in communication, radar and signal processing systems. Traditionally, such filters have been...”
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4“...-locked frequency dividers that are implemented by using standard TSMC 0.18um CMOS process . First, we...”
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5“.... The purpose of this thesis introduces the analysis frequency synthesizer and the actual design process...”
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6“... and more popular. In this thesis, the focus of research is to design the RF receiver front-end for UWB...”
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7“... in monolithic microwave integrated circuit (MMIC) process technology, more and more systems utilize the active...”
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8“...) is indispensable. Many of the applications nowadays utilize the digital signal processing to resolve...”
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9“.... The locking time can be reduced by carefully design system parameters, such as charge pump current, VCO gain...”
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10“... and is fabricated in a TSMC 0.18-μm CMOS process with 1.8 V supply voltage. The LNA employs three stages. The first...”
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11“... processes on designing planar antennas applying to UMTS, Wi-Fi and WiMAX frequency bands, theories...”
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12“... of wireless communication, cellular phone, global positioning system (GPS) and signal processing systems...”
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13“... and the 3rd wireless transmission module. The design structure, process and merchandising are analyzed...”
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14“... is a design of two chips of frequency synthesizer with tunable Gm-C loop filter. The tunable Gm-C loop...”
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15“... divider (ILFD) is proposed and implemented in a 0.18μm CMOS process, it is realized with a cross-coupled...”
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16“... to the first pipelined ADC chip design. Then, in the secondary design uses not only the op amp sharing approach...”
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17“...碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === The thesis describes the RF transceiver front-end chip design...”
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18Design of Integrated 24GHz Voltage Controlled Oscillator and 8GHz Injection Locked Frequency Divider“... frequencies, wide operating range and lower power consumption. This thesis studies the design of CMOS...”
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19“.... These two chips are fabricated by TSMC 0.18um 1.8V process. In the Chip 1 of this thesis, the digital...”
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20“... in integrated circuit technology, advanced fabrication processes are very favorable for digital design...”
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