A Framework for Generating S-Box Circuits with Boyer–Peralta Algorithm-Based Heuristics, and Its Applications to AES, SNOW3G, and Saturnin

In many lightweight cryptography applications, low area and latency are required for efficient implementation. The gate count in the cipher and the circuit depth must be low to minimize these two metrics. Many optimization strategies have been developed for the linear layer, led by the Boyer–Peralt...

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Bibliographic Details

Published in:	Transactions on Cryptographic Hardware and Embedded Systems
Main Authors:	Yongjin Jeon, Seungjun Baek, Giyoon Kim, Jongsung Kim
Format:	Article
Language:	English
Published:	Ruhr-Universität Bochum 2024-12-01
Subjects:	Lightweight cryptography S-box Low-latency implementation Circuit depth Gate count AES
Online Access:	https://tosc.iacr.org/index.php/TCHES/article/view/11940