Design Considerations for Integrated Radar Chirp Synthesizers

Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an anal...

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書誌詳細

出版年:	IEEE Access
主要な著者:	Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn
フォーマット:	論文
言語:	英語
出版事項:	IEEE 2019-01-01
主題:	Chirp linearity chirp synthesis frequency-modulated continuous-wave (FMCW) radar fully-integrated chirp synthesizer phase locked loop (PLL) phase noise
オンライン･アクセス:	https://ieeexplore.ieee.org/document/8618322/