An Area-Efficient TMR Architecture Inspired From Fast FIR Algorithm for Fault Tolerance

High-end commercial silicon chips used in aerospace and other industries utilize technology nodes at deep sub-micron levels. Efforts are underway to assess the feasibility of integrating even smaller nano-scale devices for secure communication, high-speed computing, and data storage. Due to radiatio...

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Bibliographic Details

Published in:	IEEE Access
Main Authors:	M. Deepa, P. Augusta Sophy Beulet
Format:	Article
Language:	English
Published:	IEEE 2024-01-01
Subjects:	Fault tolerant systems FIR filters fast FIR algorithm (FFA) parallel FIR filter TMR
Online Access:	https://ieeexplore.ieee.org/document/10767249/