Cryogenic InP HEMTs With Enhanced <italic>f</italic><sub>max</sub> and Reduced On-Resistance Using Double Recess

Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In...

Full description

Bibliographic Details
Published in:IEEE Journal of the Electron Devices Society
Main Authors: Yuxuan Chen, Fugui Zhou, Yongheng Gong, Yongbo Su, Wuchang Ding, Jingyuan Shi, Peng Ding, Zhi Jin
Format: Article
Language:English
Published: IEEE 2025-01-01
Subjects:
Online Access:https://ieeexplore.ieee.org/document/10948522/
Description
Summary:Cryogenic InP High-electron-mobility transistors (HEMTs)-based low-noise amplifiers (LNAs) have been applied in deep space exploration, which demands high performance from InP HEMTs. Specifically, at low temperatures, the device needs to achieve low power consumption and high operating frequency. In this study, we fabricated a double-recessed InP HEMT with a heavily doped In0.65Ga0.35As/In0.53Ga0.47As/In0.52Al0.48As multilayer cap structure to optimize the device&#x2019;s performance at low temperatures. At low temperatures, excessive on-resistance (RON) leads to increased power dissipation and also contributes to higher noise, which affects the performance of the LNAs. We employed the heavily doped In0.65Ga0.35As layer to reduce the metal-semiconductor contact resistance, thereby effectively lowering RON. Experimental results show that at 7 K, the device&#x2019;s RON is <inline-formula> <tex-math notation="LaTeX">$410~\Omega \cdot \mu $ </tex-math></inline-formula>m, which could effectively reduce the power dissipation. Additionally, we adopted a double-recessed gate structure. This structure significantly improves the device&#x2019;s maximum oscillation frequency(<inline-formula> <tex-math notation="LaTeX">$f_{\max }$ </tex-math></inline-formula>) by reducing the parasitic capacitance. At 7 K, the device&#x2019;s <inline-formula> <tex-math notation="LaTeX">$f_{\max }$ </tex-math></inline-formula> reaches 740GHz. Furthermore, the design of the second gate recess reduces the exposed area of the gate recess, which combined with the <inline-formula> <tex-math notation="LaTeX">$\rm Si_{3}N_{4}$ </tex-math></inline-formula> passivation layer, effectively suppresses the kink effect caused by surface traps at low temperatures, further improving the device&#x2019;s cryogenic performance.
ISSN:2168-6734