A simulated fabrication and characterization of a 65 nm floating-gate MOS transistor☆

The aim of this study was to virtual fabricate and characterize a Floating-gate MOS transistor of the 65 nm process. The fabrication process was designed and characterized using the TCAD Silvaco tools. In our work, a detailed flow and the parameters are proposed to virtual fabricate the complete Flo...

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書誌詳細

出版年:	Ain Shams Engineering Journal
主要な著者:	Thinh Dang Cong, Phuc Ton That Bao, Trang Hoang
フォーマット:	論文
言語:	英語
出版事項:	Elsevier 2023-04-01
主題:	Floating-gate MOS Flash memory cell Tunneling effects CMOS technology Gate leakage current TCAD tool
オンライン･アクセス:	http://www.sciencedirect.com/science/article/pii/S2090447922002283