An Approximate Adder With a Near-Normal Error Distribution: Design, Error Analysis and Practical Application

This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error metrics points to the usefulness of the propo...

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Bibliographic Details

Published in:	IEEE Access
Main Authors:	Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell, Nikos E. Mastorakis
Format:	Article
Language:	English
Published:	IEEE 2021-01-01
Subjects:	Adders approximate computing digital circuits high speed logic design low power
Online Access:	https://ieeexplore.ieee.org/document/9309208/