A high‐performance full swing 1‐bit hybrid full adder cell

Abstract This study proposes an 18‐transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR‐XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has...

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書誌詳細

出版年:	IET Circuits, Devices and Systems
主要な著者:	Shahbaz Hussain, Mehedi Hasan, Gazal Agrawal, Mohd Hasan
フォーマット:	論文
言語:	英語
出版事項:	Wiley 2022-05-01
主題:	logic gates logic design adders carry logic SPICE performance evaluation
オンライン･アクセス:	https://doi.org/10.1049/cds2.12097