Low Power Clock Generator Design With CMOS Signaling

The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (...

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發表在:	IEEE Open Journal of the Solid-State Circuits Society
Main Authors:	Yongping Fan, Ian A. Young
格式:	Article
語言:	英语
出版:	IEEE 2021-01-01
主題:	Delay locked loop phase locked loop PLL DLL phase interpolator PI
在線閱讀:	https://ieeexplore.ieee.org/document/9563068/