Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy
As semiconductor technology scales into the nanometer regime, intermittent faults have become an increasing threat. This paper focuses on the effects of intermittent faults on NET versus REG on one hand and the implications for dependability strategy on the other. First, the vulnerability characteri...
| Published in: | The Scientific World Journal |
|---|---|
| Main Authors: | , , , |
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2014-01-01
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| Online Access: | http://dx.doi.org/10.1155/2014/286084 |