A Comparative Study of Dynamic Comparators for Low-Power Successive Approximation ADC
This paper provides a critical review and the classification of comparators in low-power low-data-rate (1 kS/s~1.5 MS/s) successive approximation register analog-to-digital converters (SAR ADCs). Both voltage-domain and time-domain comparators are studied and their pros and cons are examined. The ar...
| Published in: | IEEE Open Journal of Circuits and Systems |
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| Main Author: | |
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11106380/ |