Dynamic Power Consumption In CMOS N Bit Full-Adder Circuit
This paper discusses power consumption in the full adder circuit using some fabrication technologies. Though many studies related to power consumption in the full adder circuit were performed, however, few investigations about the effect of the number of bits on the power consumption are addressed....
| Published in: | Engineering and Technology Journal |
|---|---|
| Main Authors: | , |
| Format: | Article |
| Language: | English |
| Published: |
Unviversity of Technology- Iraq
2021-05-01
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| Subjects: | |
| Online Access: | https://etj.uotechnology.edu.iq/article_169339_875450b4f4e7d55df7ab2bb7e0c451b2.pdf |