Error Correction Codes for Double Burst Errors Correction in Memories
This paper addresses the issue of double burst errors occurring in memories and presents the design of corresponding error correction codes (ECC). The proposed ECCs can correct up to two burst errors simultaneously, each up to 4-bit. The errors’ positions are randomly distributed across a...
| Published in: | IEEE Access |
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| Main Authors: | , , , , |
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11072165/ |