A Background Jitter Calibration for ADCs Using TDC Phase Information From ADPLL

The phase noise, commonly known as jitter, in Phase-Locked Loops (PLLs) is conventionally perceived as a stochastic process, necessitating a degree of tolerance in downstream circuits such as Analog-to-Digital Converters (ADCs). This paper addresses this issue within the context of a Time-to-Digital...

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發表在:	IEEE Access
Main Authors:	Haoyang Shen, Hao Zheng, Daniel O'Hare, Deepu John, Barry Cardiff
格式:	Article
語言:	英语
出版:	IEEE 2024-01-01
主題:	ADC jitter calibration ADPLL non-uniform sampling interpolation algorithm digital signal processing
在線閱讀:	https://ieeexplore.ieee.org/document/10759641/