VLSI implementation of AES algorithm against differential power attack and differential fault attack

A VLSI implementation of AES algorithm against both differential power attack and differential fault attack was proposed. The main countermeasures employed in this hardware design are masking technique and two-dimensional parity-based concurrent error detection method. And exploits such methods as s...

詳細記述

書誌詳細

出版年:	Tongxin xuebao
主要な著者:	HAN Jun, ZENG Xiao-yang, ZHAO Jia
フォーマット:	論文
言語:	中国語
出版事項:	Editorial Department of Journal on Communications 2010-01-01
主題:	information security anti-attack algorithm VLSI implementation side channel attack AES
オンライン･アクセス:	http://www.joconline.com.cn/zh/article/74650743/