Custom Soft-Core RISC Processor Validation Based on Real-Time Event Handling Scheduler FPGA Implementation

In dynamic real-time systems (RTS), the synchronous communication model is a source of unpredictable behaviors caused by the difficulty of estimating the maximum lockdown time in a process. Inter-task communication is a critical issue in RTS, even in the case of uniprocessor architectures. Using an...

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Bibliographic Details

Published in:	IEEE Access
Main Authors:	Ionel Zagan, Vasile Gheorghita Gaitan
Format:	Article
Language:	English
Published:	IEEE 2023-01-01
Subjects:	Hardware RTOS microprocessor scheduling field-programmable gate arrays (FPGA) real-time systems
Online Access:	https://ieeexplore.ieee.org/document/10098567/