FPGA‐based implementation of floating point processing element for the design of efficient FIR filters

Abstract Numerous applications based on very large scale intergration (VLSI) architecture suffer from large size components that lead to an error in the design of the filter during the stages of floating point arithmetic. Hence, it is necessary to change the architectural model that increases the de...

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Bibliographic Details

Published in:	IET Computers & Digital Techniques
Main Authors:	Tintu Mary John, Shanty Chacko
Format:	Article
Language:	English
Published:	Wiley 2021-07-01
Subjects:	delays field programmable gate arrays FIR filters floating point arithmetic VLSI
Online Access:	https://doi.org/10.1049/cdt2.12010