Low power area efficient self-gated flip flop: Design, implementation and analysis in emerging devices

This study presents a novel CMOS self-gated flip flop for low power and area efficient applications. The low power operations are achieved by deactivating the clock signal when not required in the circuit. The study explores the proposed design in emergingdevices like Carbon Nanotube Field Ef...

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Bibliographic Details

Published in:	Engineering and Applied Science Research
Main Authors:	Owais Ahmad Shah, Geeta Nijhawan, Imran Ahmed Khan
Format:	Article
Language:	English
Published:	Khon Kaen University 2022-11-01
Subjects:	self-gated cmos digital circuit cntfet gnrfet finfet
Online Access:	https://ph01.tci-thaijo.org/index.php/easr/article/view/248964/169945