Simulation and Performance Analysis of 32 nm FinFet based 4-Bit Carry Look Adder
FinFET at 32 nm and beyond is an emerging transistor technology offer interesting delay–power tradeoff. FinFETs are a necessary step in the evolution of semiconductors because bulk CMOS has difficulties in scaling beyond 32 nm. Use of the back gate leads to very interesting design opportunities....
| Published in: | Журнал нано- та електронної фізики |
|---|---|
| Main Authors: | S. Rashid, S. Khan, A. Singh |
| Format: | Article |
| Language: | English |
| Published: |
Sumy State University
2017-10-01
|
| Subjects: | |
| Online Access: | http://jnep.sumdu.edu.ua:8080/download/numbers/2017/5/articles/Proof_JNEP_05003.pdf |
Similar Items
Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET
by: Myoungsu Son, et al.
Published: (2023-01-01)
by: Myoungsu Son, et al.
Published: (2023-01-01)
The Effect of Fin Structure in 5 nm FinFET Technology
by: Enming Shang, et al.
Published: (2019-12-01)
by: Enming Shang, et al.
Published: (2019-12-01)
An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs
by: Qamar-Ud-Din Memon, et al.
Published: (2024-01-01)
by: Qamar-Ud-Din Memon, et al.
Published: (2024-01-01)
Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application
by: Danian Dong, et al.
Published: (2023-11-01)
by: Danian Dong, et al.
Published: (2023-11-01)
Performance and Reliability Assessment of Schottky Complementary Multi-FinFET Inverter for Advanced Scaling Nodes
by: Shalini Virumandi, et al.
Published: (2025-01-01)
by: Shalini Virumandi, et al.
Published: (2025-01-01)
BSIM—SPICE Models Enable FinFET and UTB IC Designs
by: Navid Paydavosi, et al.
Published: (2013-01-01)
by: Navid Paydavosi, et al.
Published: (2013-01-01)
Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance
by: Priyanka Agrwal, et al.
Published: (2025-02-01)
by: Priyanka Agrwal, et al.
Published: (2025-02-01)
Performance assessment of InGaAs–SOI–FinFET for enhancing switching capability using high-k dielectric
by: Priyanka Agrwal, et al.
Published: (2024-08-01)
by: Priyanka Agrwal, et al.
Published: (2024-08-01)
Analog Performance and its Variability in Sub-10 nm Fin-Width FinFETs: a Detailed Analysis
by: Mandar S. Bhoir, et al.
Published: (2019-01-01)
by: Mandar S. Bhoir, et al.
Published: (2019-01-01)
Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs
by: Peng Lu, et al.
Published: (2021-12-01)
by: Peng Lu, et al.
Published: (2021-12-01)
Reliability analysis of a CNT-TF-FinFET for hostile temperature
by: Praween Kumar Srivastava, et al.
Published: (2023-12-01)
by: Praween Kumar Srivastava, et al.
Published: (2023-12-01)
Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs
by: Kazuhiko Endo, et al.
Published: (2014-05-01)
by: Kazuhiko Endo, et al.
Published: (2014-05-01)
Comprehensive Investigation of Truncated Fin GaN FinFET for Improved Analog/RF Performance
by: Praween Kumar Srivastava, et al.
Published: (2025-01-01)
by: Praween Kumar Srivastava, et al.
Published: (2025-01-01)
A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications
by: Meysam Zareiee, et al.
Published: (2025-07-01)
by: Meysam Zareiee, et al.
Published: (2025-07-01)
High-Drain Field Impacting Channel-Length Modulation Effect for Nano-Node N-Channel FinFETs
by: Mu-Chun Wang, et al.
Published: (2021-03-01)
by: Mu-Chun Wang, et al.
Published: (2021-03-01)
Risks of Silent Data Corruption Due to the Combined Effects of Latent Faults and Aging Phenomena Affecting FinFET-Based ICs
by: Martin Omana, et al.
Published: (2025-01-01)
by: Martin Omana, et al.
Published: (2025-01-01)
Degradation Measurement and Modelling under Ageing in a 16 nm FinFET FPGA
by: Justin Sobas, et al.
Published: (2023-12-01)
by: Justin Sobas, et al.
Published: (2023-12-01)
Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection
by: Xinyu Zhu, et al.
Published: (2022-05-01)
by: Xinyu Zhu, et al.
Published: (2022-05-01)
Design Exploration of 14 nm FinFET for Energy-Efficient Cryogenic Computing
by: Amol D. Gaidhane, et al.
Published: (2023-01-01)
by: Amol D. Gaidhane, et al.
Published: (2023-01-01)
Source/Drain Patterning FinFETs as Solution for Physical Area Scaling Toward 5-nm Node
by: Jun-Sik Yoon, et al.
Published: (2019-01-01)
by: Jun-Sik Yoon, et al.
Published: (2019-01-01)
Optimization of Multi-Fins FinFET Implemented on SOI Wafer Based on SiGe and Gaussian Process Regression
by: Christofer N. Yalung, et al.
Published: (2024-01-01)
by: Christofer N. Yalung, et al.
Published: (2024-01-01)
A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET
by: Yan Zheng, et al.
Published: (2021-01-01)
by: Yan Zheng, et al.
Published: (2021-01-01)
A Dual Core Source/Drain GAA FinFET
by: Prachuryya Subash Das, et al.
Published: (2023-06-01)
by: Prachuryya Subash Das, et al.
Published: (2023-06-01)
High-Performance and Energy-Efficient Leaky Integrate-and-Fire Neuron and Spike Timing-Dependent Plasticity Circuits in 7nm FinFET Technology
by: Mohammad Khaleqi Qaleh Jooq, et al.
Published: (2023-01-01)
by: Mohammad Khaleqi Qaleh Jooq, et al.
Published: (2023-01-01)
Systematic DC/AC Performance Benchmarking of Sub-7-nm Node FinFETs and Nanosheet FETs
by: Jun-Sik Yoon, et al.
Published: (2018-01-01)
by: Jun-Sik Yoon, et al.
Published: (2018-01-01)
Design and investigation of a delay controlled ALU employing FinFET& CNTFET technologies
by: Ch JayaPrakash, et al.
Published: (2025-09-01)
by: Ch JayaPrakash, et al.
Published: (2025-09-01)
Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes
by: Daniel Nagy, et al.
Published: (2020-01-01)
by: Daniel Nagy, et al.
Published: (2020-01-01)
Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs
by: Buqing Xu, et al.
Published: (2022-04-01)
by: Buqing Xu, et al.
Published: (2022-04-01)
Cryogenic Performance and Modeling of Sub-5nm Fin-Width Bulk FinFETs for Quantum Computing Applications
by: Deepesh Sharma, et al.
Published: (2025-01-01)
by: Deepesh Sharma, et al.
Published: (2025-01-01)
Detectors Array for In Situ Electron Beam Imaging by 16-nm FinFET CMOS Technology
by: Chien-Ping Wang, et al.
Published: (2021-05-01)
by: Chien-Ping Wang, et al.
Published: (2021-05-01)
Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications
by: Mahmoud S. Badran, et al.
Published: (2019-01-01)
by: Mahmoud S. Badran, et al.
Published: (2019-01-01)
3D Simulation for Melt Laser Anneal Integration in FinFET’s Contact
by: Toshiyuki Tabata, et al.
Published: (2020-01-01)
by: Toshiyuki Tabata, et al.
Published: (2020-01-01)
Embedded Micro-detectors for EUV Exposure Control in FinFET CMOS Technology
by: Chien-Ping Wang, et al.
Published: (2022-01-01)
by: Chien-Ping Wang, et al.
Published: (2022-01-01)
Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
by: Soohyun Kim, et al.
Published: (2020-04-01)
by: Soohyun Kim, et al.
Published: (2020-04-01)
Simulation Study on the Charge Collection Mechanism of FinFET Devices in Single-Event Upset
by: Hongwei Zhang, et al.
Published: (2024-01-01)
by: Hongwei Zhang, et al.
Published: (2024-01-01)
Cryogenic Embedded System to Support Quantum Computing: From 5-nm FinFET to Full Processor
by: Paul R. Genssler, et al.
Published: (2023-01-01)
by: Paul R. Genssler, et al.
Published: (2023-01-01)
RF Performance Benchmark of Nanosheets, Nanowires, FinFETs, and TreeFETs
by: Hsin-Cheng Lin, et al.
Published: (2024-01-01)
by: Hsin-Cheng Lin, et al.
Published: (2024-01-01)
A low power design using FinFET based adiabatic switching principle: Application to 16-Bit arithmetic logic unit
by: Reginald H. Vanlalchaka, et al.
Published: (2023-04-01)
by: Reginald H. Vanlalchaka, et al.
Published: (2023-04-01)
Analysis of Circuit Simulation Considering Total Ionizing Dose Effects on FinFET and Nanowire FET
by: Hyeonjae Won, et al.
Published: (2021-01-01)
by: Hyeonjae Won, et al.
Published: (2021-01-01)
The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FinFET
by: Wen-Qi Zhang, et al.
Published: (2023-04-01)
by: Wen-Qi Zhang, et al.
Published: (2023-04-01)
Similar Items
-
Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET
by: Myoungsu Son, et al.
Published: (2023-01-01) -
The Effect of Fin Structure in 5 nm FinFET Technology
by: Enming Shang, et al.
Published: (2019-12-01) -
An Efficient Technique to Simulate the AC/DC Parameters of Trigate FinFETs
by: Qamar-Ud-Din Memon, et al.
Published: (2024-01-01) -
Systematical Investigation of Flicker Noise in 14 nm FinFET Devices towards Stochastic Computing Application
by: Danian Dong, et al.
Published: (2023-11-01) -
Performance and Reliability Assessment of Schottky Complementary Multi-FinFET Inverter for Advanced Scaling Nodes
by: Shalini Virumandi, et al.
Published: (2025-01-01)
