A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS

A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock distribution, a common bootstra...

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发表在:	IEEE Access
Main Authors:	Hamid Karrari, Pietro Andreani, Siyu Tan
格式:	文件
语言:	英语
出版:	IEEE 2024-01-01
主题:	Analog-to-digital converter (ADC) CMOS comparator bootstrapped switch dynamic amplifier (DA) asynchronous SAR
在线阅读:	https://ieeexplore.ieee.org/document/10477955/